-- Simulation model for Xilinx block ram with initial values.
-- To be used in conjunction with digital_dc2.
-- 5/18/05 AZ

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAMB16_S9_S9 is port (
		 DOA : out std_logic_vector (7 downto 0);
         DOPA : out std_logic_vector (0 downto 0);
         ADDRA : in std_logic_vector (10 downto 0);
         CLKA : in std_logic;
         DIA : in std_logic_vector (7 downto 0);
         DIPA : in std_logic_vector (0 downto 0);
         ENA : in std_logic;
         SSRA : in std_logic;
         WEA : in std_logic;
		 DOB : out std_logic_vector (7 downto 0);
         DOPB : out std_logic_vector (0 downto 0);
         ADDRB : in std_logic_vector (10 downto 0);
         CLKB : in std_logic;
         DIB : in std_logic_vector (7 downto 0);
         DIPB : in std_logic_vector (0 downto 0);
         ENB : in std_logic;
         SSRB : in std_logic;
         WEB : in std_logic
);
end entity;


ARCHITECTURE behavior OF RAMB16_S9_S9 IS

-- signals
signal MEMADDRA: integer range 0 to 2047;
signal MEMADDRB: integer range 0 to 2047;
signal MEMADDRA_D: integer range 0 to 2047;
signal MEMADDRB_D: integer range 0 to 2047;



 
BEGIN

MEMADDRA <= conv_integer(ADDRA);
MEMADDRB <= conv_integer(ADDRB);

mem_process_001 : process (CLKA, MEMADDRA, ENA)
begin
	if rising_edge(CLKA) then 
		if(ENA = '1') then
			MEMADDRA_D <= MEMADDRA;
		end if;
	end if;
end process;

mem_process_002 : process (CLKB, MEMADDRB, ENB)
begin
	if rising_edge(CLKB) then 
		if(ENB = '1') then
			MEMADDRB_D <= MEMADDRB;
		end if;
	end if;
end process;


mem_process : process (CLKA, CLKB, MEMADDRA, MEMADDRB,  DIA, DIPA, DIB, DIPB, 
	ENA, ENB, WEA, WEB, MEMADDRA_D, MEMADDRB_D)
variable  MEM : std_logic_vector(16383 downto 0);
variable MEMP : std_logic_vector(2047 downto 0);

      begin
      
      if rising_edge(CLKA) then 
      	if(WEA = '1') and (ENA = '1') then
            MEM((8*(MEMADDRA+1) -1) downto (8*MEMADDRA)):= DIA;
			MEMP(MEMADDRA downto MEMADDRA) := DIPA;  
	   	end if;
        if(WEB = '1') and (ENB = '1') then
            MEM((8*(MEMADDRB+1) -1) downto (8*MEMADDRB)):= DIB;
			MEMP(MEMADDRB downto MEMADDRB) := DIPB;
        end if;
	  end if;
	   
     
		DOA <= MEM((8*(MEMADDRA_D+1) -1) downto (8*MEMADDRA_D));
		DOPA <= MEMP(MEMADDRA_D downto MEMADDRA_D);
		DOB <= MEM((8*(MEMADDRB_D+1) -1) downto (8*MEMADDRB_D));
		DOPB <= MEMP(MEMADDRB_D downto MEMADDRB_D);


end process;

 
END behavior;
