-- Objective: test a few basic inputs/outputs for the FFT_RADIX2_4 radix-2/radix-4 butterflies.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_FFT_RADIX2_4 is end test_FFT_RADIX2_4;

architecture testbench of test_FFT_RADIX2_4 is

-- Declaration of the component under test
	COMPONENT FFT_RADIX2_4
	PORT(
		CLK : IN std_logic;
		SAMPLE_CLK_IN : IN std_logic;
		X1A : IN std_logic_vector(17 downto 0);
		X1B : IN std_logic_vector(17 downto 0);
		X1C : IN std_logic_vector(17 downto 0);
		X1D : IN std_logic_vector(17 downto 0);
		Y1A : IN std_logic_vector(17 downto 0);
		Y1B : IN std_logic_vector(17 downto 0);
		Y1C : IN std_logic_vector(17 downto 0);
		Y1D : IN std_logic_vector(17 downto 0);
		CB : IN std_logic_vector(17 downto 0);
		CC : IN std_logic_vector(17 downto 0);
		CD : IN std_logic_vector(17 downto 0);
		SB : IN std_logic_vector(17 downto 0);
		SC : IN std_logic_vector(17 downto 0);
		SD : IN std_logic_vector(17 downto 0);
		OUTPUT_SHIFT : IN std_logic_vector(1 downto 0);
		RADIX2_4N : IN std_logic;          
		X2A : OUT std_logic_vector(17 downto 0);
		X2B : OUT std_logic_vector(17 downto 0);
		X2C : OUT std_logic_vector(17 downto 0);
		X2D : OUT std_logic_vector(17 downto 0);
		Y2A : OUT std_logic_vector(17 downto 0);
		Y2B : OUT std_logic_vector(17 downto 0);
		Y2C : OUT std_logic_vector(17 downto 0);
		Y2D : OUT std_logic_vector(17 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic;
		OVERFLOW : OUT std_logic
		);
	END COMPONENT;

signal   OVERFLOW : std_logic;
signal   RADIX2_4N : std_logic;
signal   SAMPLE_CLK_OUT : std_logic;
signal   Y2D : std_logic_vector(17 downto 0);
signal   Y2C : std_logic_vector(17 downto 0);
signal   Y2B : std_logic_vector(17 downto 0);
signal   Y2A : std_logic_vector(17 downto 0);
signal   X2D : std_logic_vector(17 downto 0);
signal   X2C : std_logic_vector(17 downto 0);
signal   X2B : std_logic_vector(17 downto 0);
signal   X2A : std_logic_vector(17 downto 0);
signal   OUTPUT_SHIFT : std_logic_vector(1 downto 0);
signal   SD : std_logic_vector(17 downto 0);
signal   SC : std_logic_vector(17 downto 0);
signal   SB : std_logic_vector(17 downto 0);
signal   CD : std_logic_vector(17 downto 0);
signal   CC : std_logic_vector(17 downto 0);
signal   CB : std_logic_vector(17 downto 0);
signal   Y1D : std_logic_vector(17 downto 0);
signal   Y1C : std_logic_vector(17 downto 0);
signal   Y1B : std_logic_vector(17 downto 0);
signal   Y1A : std_logic_vector(17 downto 0);
signal   X1D : std_logic_vector(17 downto 0);
signal   X1C : std_logic_vector(17 downto 0);
signal   X1B : std_logic_vector(17 downto 0);
signal   X1A : std_logic_vector(17 downto 0);
signal   SAMPLE_CLK_IN : std_logic;
signal   CLK : std_logic;

begin

-- Place stimulus and analysis statements here      
process
begin
	CLK <= '1';
	wait for 5 ns;
	CLK <= '0';
	wait for 5 ns;
end process;

process
begin
	SAMPLE_CLK_IN <= '0'; 
	X1A <= (others => '0');
	Y1A <= (others => '0');
	X1B <= (others => '0');
	Y1B <= (others => '0');
	X1C <= (others => '0');
	Y1C <= (others => '0');
	X1D <= (others => '0');
	Y1D <= (others => '0');
	CB <= "011111111111111111";
	CC <= "000000000000000000";
	CD <= "000000000000000000";
	SB <= "000000000000000000";
	SC <= "000000000000000000";
	SD <= "000000000000000000";
	wait for 105 ns;
	SAMPLE_CLK_IN <= '1'; 
	X1A <= (17 => '1', others => '0');
	Y1A <= (others => '0');
	X1B <= (others => '0');
	Y1B <= (others => '0');
	X1C <= (others => '0');
	Y1C <= (others => '0');
	X1D <= (others => '0');
	Y1D <= (others => '0');
	wait for 10 ns;
	SAMPLE_CLK_IN <= '0'; 
	wait for 15 ns;
end process;
		
	
RADIX2_4N <= '1';
OUTPUT_SHIFT <= "00";



dut :  FFT_RADIX2_4  port map (
     OVERFLOW => OVERFLOW,
     RADIX2_4N => RADIX2_4N,
     SAMPLE_CLK_OUT => SAMPLE_CLK_OUT,
     Y2D => Y2D,
     Y2C => Y2C,
     Y2B => Y2B,
     Y2A => Y2A,
     X2D => X2D,
     X2C => X2C,
     X2B => X2B,
     X2A => X2A,
     OUTPUT_SHIFT => OUTPUT_SHIFT,
     SD => SD,
     SC => SC,
     SB => SB,
     CD => CD,
     CC => CC,
     CB => CB,
     Y1D => Y1D,
     Y1C => Y1C,
     Y1B => Y1B,
     Y1A => Y1A,
     X1D => X1D,
     X1C => X1C,
     X1B => X1B,
     X1A => X1A,
     SAMPLE_CLK_IN => SAMPLE_CLK_IN,
     CLK => CLK
      );

end testbench;
