----------------------------------------------
-- MSS copyright 2001
-- Filename: LFSR11.VHD
-- Author: Angela Baran / MSS
-- Inheritance: none
-- Edit date: 7-29-02
-- Revision: 0.004
-- Description: 
--		pseudo random bit generation. based on 11-bit linear feedback
-- 	shift register. A synchronous reset is provided to reset
--		the PN sequence at frame boundaries.
--
-- Rev 0.002 AZ
-- 	Added synchronous reset 
--
-- Rev 0.003 AZ 9-14-01
-- Added bit clk out
--
-- Rev 0.004 AZ 7-29-02
-- added SOF output.
---------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LFSR11 is
  port (
	ASYNC_RESET: in std_logic;
		-- asynchronous reset, active high
	CLK: in  std_logic;   
		-- clock synchronous
	BIT_CLK_REQ: in std_logic;
		-- request for output bit, 
		-- read output bit at rising_edge of CLK and BIT_CLK_REQ_D = '1'
	SYNC_RESET: in std_logic;
		-- synchronous reset for linear feedback shift register.
		-- 1 CLK wide pulse aligned with BIT_CLK_REQ.

	SOF_OUT: out std_logic;
		-- '1' when LFSR is all zeros.
	BIT_CLK_OUT: out std_logic;
	LFSR_BIT: out std_logic	
		-- Linear feedback shift register output. Read at rising edge of CLK
		-- when BIT_CLK_OUT = '1'
    );
end LFSR11;

architecture behavior of LFSR11 is

-----------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------
signal LFSR_REG     : std_logic_vector(10 downto 0);

-----------------------------------------------------------------
-- IMPLEMENTATION
-----------------------------------------------------------------
begin

-- linear feedback shift register
LSFR_GEN: process(ASYNC_RESET, CLK)
begin
if (ASYNC_RESET = '1') then
	LFSR_REG     <= (others => '0');
   LFSR_BIT <= '0';
	SOF_OUT <= '0';
elsif rising_edge(CLK) then
	BIT_CLK_OUT <= BIT_CLK_REQ;

	if(SYNC_RESET = '1') then
		-- synchronous reset
		LFSR_REG     <= (others => '0');
	   LFSR_BIT <= '0';
		SOF_OUT <= '1';
	elsif(BIT_CLK_REQ = '1') then
		-- prepare next bit; used Xilinx XAP 052 Table 3 for taps
		LFSR_REG(10 downto 1) <= LFSR_REG(9 downto 0); 
		LFSR_REG(0)  <= not (LFSR_REG(10) xor LFSR_REG(8));
		LFSR_BIT <= LFSR_REG(10);
		if(LFSR_REG = "00000000000") then
			SOF_OUT <= '1';
	  	else 
			SOF_OUT <= '0';
	 	end if;
	end if;
end if;
end process;
    
end behavior;

