-- Simulation model for Xilinx block ram with initial values.
-- To be used in conjunction with digital_dc2.
-- 5/18/05 AZ

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAMB16_S18_S18SIN is port (
			DOA : out std_logic_vector (15 downto 0);
         DOPA : out std_logic_vector (1 downto 0);
         ADDRA : in std_logic_vector (9 downto 0);
         CLKA : in std_logic;
         DIA : in std_logic_vector (15 downto 0);
         DIPA : in std_logic_vector (1 downto 0);
         ENA : in std_logic;
         SSRA : in std_logic;
         WEA : in std_logic;
			DOB : out std_logic_vector (15 downto 0);
         DOPB : out std_logic_vector (1 downto 0);
         ADDRB : in std_logic_vector (9 downto 0);
         CLKB : in std_logic;
         DIB : in std_logic_vector (15 downto 0);
         DIPB : in std_logic_vector (1 downto 0);
         ENB : in std_logic;
         SSRB : in std_logic;
         WEB : in std_logic
);
end entity;


ARCHITECTURE behavior OF RAMB16_S18_S18SIN IS

-- signals
signal MEMADDRA: integer range 0 to 1023;
signal MEMADDRB: integer range 0 to 1023;

constant INIT_00: std_logic_vector(255 downto 0) := x"0bc80aff0a36096d08a407db07110648057f04b603ed0324025b019200c90000";
constant INIT_01: std_logic_vector(255 downto 0) := x"1857178e16c515fc1533146a13a112d8120f1147107e0fb50eec0e230d5a0c91";
constant INIT_02: std_logic_vector(255 downto 0) := x"24e224192351228821bf20f7202e1f651e9d1dd41d0b1c431b7a1ab119e8191f";
constant INIT_03: std_logic_vector(255 downto 0) := x"3167309f2fd72f0f2e462d7e2cb62bee2b252a5d299528cc2804273b267325aa";
constant INIT_04: std_logic_vector(255 downto 0) := x"3de53d1d3c563b8e3ac639ff3937386f37a736df3617354f348733bf32f7322f";
constant INIT_05: std_logic_vector(255 downto 0) := x"4a59499248cb4804473d467645af44e844214359429241cb4103403c3f743ead";
constant INIT_06: std_logic_vector(255 downto 0) := x"56c255fc5536546f53a952e3521c5156508f4fc94f024e3b4d754cae4be74b20";
constant INIT_07: std_logic_vector(255 downto 0) := x"631e6258619360ce60085f435e7d5db75cf25c2c5b665aa059da5914584e5788";
constant INIT_08: std_logic_vector(255 downto 0) := x"6f6a6ea66de16d1d6c586b946acf6a0b6946688167bc66f76632656d64a863e3";
constant INIT_09: std_logic_vector(255 downto 0) := x"7ba57ae27a1e795b789877d47711764d758a74c67402733e727a71b670f2702e";
constant INIT_0A: std_logic_vector(255 downto 0) := x"87cd870b8649858784c584028340827e81bb80f980367f737eb17dee7d2b7c68";
constant INIT_0B: std_logic_vector(255 downto 0) := x"93e0931f925f919e90dd901c8f5b8e9a8dd98d188c568b958ad48a128950888f";
constant INIT_0C: std_logic_vector(255 downto 0) := x"9fdc9f1d9e5e9d9e9cdf9c209b609aa199e19921986197a196e19621956194a0";
constant INIT_0D: std_logic_vector(255 downto 0) := x"abbfab02aa44a987a8c9a80ba74da68fa5d1a513a454a396a2d7a219a15aa09b";
constant INIT_0E: std_logic_vector(255 downto 0) := x"b789b6cdb611b555b499b3ddb320b264b1a7b0ebb02eaf71aeb4adf7ad3aac7d";
constant INIT_0F: std_logic_vector(255 downto 0) := x"c335c27bc1c1c107c04dbf92bed8be1dbd63bca8bbedbb32ba76b9bbb900b844";
constant INIT_10: std_logic_vector(255 downto 0) := x"cec4ce0ccd54cc9ccbe3cb2bca72c9b9c900c847c78ec6d5c61cc562c4a9c3ef";
constant INIT_11: std_logic_vector(255 downto 0) := x"da33d97dd8c7d810d75ad6a4d5edd536d47fd3c8d311d25ad1a3d0ebd034cf7c";
constant INIT_12: std_logic_vector(255 downto 0) := x"e580e4cce418e364e2b0e1fbe147e092dfdedf29de74ddbedd09dc54db9edae9";
constant INIT_13: std_logic_vector(255 downto 0) := x"f0aaeff8ef46ee94ede3ed30ec7eebcceb19ea67e9b4e901e84ee79ae6e7e633";
constant INIT_14: std_logic_vector(255 downto 0) := x"fbaefafffa50f9a0f8f1f841f791f6e1f631f580f4d0f41ff36ef2bdf20cf15b";
constant INIT_15: std_logic_vector(255 downto 0) := x"068c05df0532048503d8032b027d01d001220074ffc6ff18fe69fdbbfd0cfc5d";
constant INIT_16: std_logic_vector(255 downto 0) := x"114110970fed0f420e980ded0d420c970bec0b400a9509e9093d089107e50738";
constant INIT_17: std_logic_vector(255 downto 0) := x"1bcc1b251a7d19d6192e188617dd1735168c15e3153a149113e8133f129511eb";
constant INIT_18: std_logic_vector(255 downto 0) := x"262c258724e2243d239822f3224d21a82102205c1fb51f0f1e681dc21d1b1c74";
constant INIT_19: std_logic_vector(255 downto 0) := x"305e2fbc2f1a2e782dd62d332c912bee2b4b2aa72a04296028bd2819277526d0";
constant INIT_1A: std_logic_vector(255 downto 0) := x"3a6139c23923388437e5374536a53606356534c53425338432e3324231a130ff";
constant INIT_1B: std_logic_vector(255 downto 0) := x"4434439842fc426041c44127408a3fee3f513eb33e163d783cda3c3c3b9e3b00";
constant INIT_1C: std_logic_vector(255 downto 0) := x"4dd44d3c4ca34c0a4b714ad84a3e49a4490a487047d6473b46a14606456b44cf";
constant INIT_1D: std_logic_vector(255 downto 0) := x"574156ac5617558154eb545553bf5328529151fb516350cc50354f9d4f054e6d";
constant INIT_1E: std_logic_vector(255 downto 0) := x"607a5fe85f565ec35e315d9e5d0b5c785be45b515abd5a2959955900586b57d7";
constant INIT_1F: std_logic_vector(255 downto 0) := x"697c68ed685e67cf674066b1662165926502647163e1635062bf622e619d610b";
constant INIT_20: std_logic_vector(255 downto 0) := x"724671bb713070a470196f8d6f016e746de86d5b6cce6c416bb36b266a986a0a";
constant INIT_21: std_logic_vector(255 downto 0) := x"7ad77a4f79c8794078b8783077a7771e7696760c758374f9746f73e5735b72d1";
constant INIT_22: std_logic_vector(255 downto 0) := x"832d82aa822681a2811d809980147f8f7f0a7e847dfe7d787cf27c6c7be57b5e";
constant INIT_23: std_logic_vector(255 downto 0) := x"8b488ac88a4889c8894788c6884587c4874286c1863f85bc853a84b7843483b1";
constant INIT_24: std_logic_vector(255 downto 0) := x"932692aa922e91b1913590b8903a8fbd8f3f8ec18e438dc48d468cc78c478bc8";
constant INIT_25: std_logic_vector(255 downto 0) := x"9ac69a4e99d6995d98e4986b97f2977896fe9684960a958f95149499941e93a2";
constant INIT_26: std_logic_vector(255 downto 0) := x"a227a1b2a13ea0c9a0549fdf9f6a9ef49e7e9e089d929d1b9ca49c2d9bb69b3e";
constant INIT_27: std_logic_vector(255 downto 0) := x"a947a8d6a866a7f6a785a714a6a2a631a5bfa54da4daa468a3f5a382a30ea29a";
constant INIT_28: std_logic_vector(255 downto 0) := x"b025afb9af4daee0ae74ae07ad99ad2cacbeac50abe2ab73ab04aa95aa26a9b6";
constant INIT_29: std_logic_vector(255 downto 0) := x"b6c1b659b5f1b589b520b4b7b44eb3e5b37bb311b2a7b23db1d2b167b0fcb091";
constant INIT_2A: std_logic_vector(255 downto 0) := x"bd19bcb5bc52bbedbb89bb25bac0ba5bb9f5b990b92ab8c4b85db7f6b78fb728";
constant INIT_2B: std_logic_vector(255 downto 0) := x"c32cc2cdc26ec20ec1aec14ec0edc08cc02bbfcabf68bf06bea4be42bddfbd7c";
constant INIT_2C: std_logic_vector(255 downto 0) := x"c8fac89fc844c7e9c78dc731c6d5c679c61cc5bfc562c504c4a6c448c3eac38b";
constant INIT_2D: std_logic_vector(255 downto 0) := x"ce82ce2bcdd5cd7ecd26cccfcc77cc1fcbc7cb6ecb15cabcca63ca09c9afc955";
constant INIT_2E: std_logic_vector(255 downto 0) := x"d3c2d370d31ed2cbd278d225d1d2d17ed12bd0d6d082d02dcfd8cf83cf2eced8";
constant INIT_2F: std_logic_vector(255 downto 0) := x"d8bad86cd81fd7d1d782d734d6e5d696d647d5f7d5a7d557d506d4b6d465d413";
constant INIT_30: std_logic_vector(255 downto 0) := x"dd69dd20dcd7dc8ddc44dbfadbb0db65db1adacfda84da38d9ecd9a0d954d907";
constant INIT_31: std_logic_vector(255 downto 0) := x"e1cee18ae146e101e0bce076e031dfebdfa5df5edf17ded0de89de41ddf9ddb1";
constant INIT_32: std_logic_vector(255 downto 0) := x"e5e9e5aae56ae52ae4eae4a9e468e427e3e5e3a3e361e31fe2dce299e256e212";
constant INIT_33: std_logic_vector(255 downto 0) := x"e9bae97fe944e908e8cde891e854e818e7dbe79ee760e722e6e4e6a6e667e629";
constant INIT_34: std_logic_vector(255 downto 0) := x"ed3eed08ecd2ec9bec64ec2debf5ebbeeb85eb4deb14eadbeaa2ea68ea2ee9f4";
constant INIT_35: std_logic_vector(255 downto 0) := x"f077f046f014efe2efb0ef7def4bef18eee4eeb0ee7cee48ee14eddfedaaed74";
constant INIT_36: std_logic_vector(255 downto 0) := x"f363f337f30af2ddf2aff281f253f225f1f7f1c8f198f169f139f109f0d9f0a8";
constant INIT_37: std_logic_vector(255 downto 0) := x"f602f5daf5b2f58af562f539f510f4e6f4bcf492f468f43df412f3e7f3bbf38f";
constant INIT_38: std_logic_vector(255 downto 0) := x"f854f831f80ef7eaf7c7f7a3f77ef75af735f70ff6eaf6c4f69ef677f651f629";
constant INIT_39: std_logic_vector(255 downto 0) := x"fa58fa3afa1bf9fdf9def9bff99ff980f95ff93ff91ef8fdf8dcf8baf899f876";
constant INIT_3A: std_logic_vector(255 downto 0) := x"fc0efbf4fbdbfbc1fba7fb8dfb72fb58fb3cfb21fb05fae9faccfab0fa93fa75";
constant INIT_3B: std_logic_vector(255 downto 0) := x"fd75fd61fd4cfd38fd22fd0dfcf7fce1fccbfcb4fc9efc86fc6ffc57fc3ffc26";
constant INIT_3C: std_logic_vector(255 downto 0) := x"fe8efe7ffe6ffe5ffe4ffe3ffe2efe1dfe0bfdfafde8fdd5fdc3fdb0fd9cfd89";
constant INIT_3D: std_logic_vector(255 downto 0) := x"ff58ff4eff43ff38ff2dff21ff16ff09fefdfef0fee3fed6fec8febafeabfe9d";
constant INIT_3E: std_logic_vector(255 downto 0) := x"ffd3ffceffc8ffc2ffbcffb5ffaeffa7ffa0ff98ff90ff87ff7eff75ff6cff62";
constant INIT_3F: std_logic_vector(255 downto 0) := x"fffffffffffffffefffcfffafff8fff6fff4fff1ffedffeaffe6ffe2ffddffd9";

-- The 2-bit INITP_XX stores the 2 MSbs of the 18-bit filter coefficients.
constant INITP_00: std_logic_vector(255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant INITP_01: std_logic_vector(255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant INITP_02: std_logic_vector(255 downto 0) := x"5555555555555555555550000000000000000000000000000000000000000000";
constant INITP_03: std_logic_vector(255 downto 0) := x"5555555555555555555555555555555555555555555555555555555555555555";
constant INITP_04: std_logic_vector(255 downto 0) := x"5555555555555555555555555555555555555555555555555555555555555555";
constant INITP_05: std_logic_vector(255 downto 0) := x"5555555555555555555555555555555555555555555555555555555555555555";
constant INITP_06: std_logic_vector(255 downto 0) := x"5555555555555555555555555555555555555555555555555555555555555555";
constant INITP_07: std_logic_vector(255 downto 0) := x"5555555555555555555555555555555555555555555555555555555555555555";




 
BEGIN

MEMADDRA <= conv_integer(ADDRA);
MEMADDRB <= conv_integer(ADDRB);


mem_process : process (CLKA, CLKB, MEMADDRA, MEMADDRB,  DIA, DIPA, DIB, DIPB, 
	ENA, ENB, WEA, WEB)
variable  MEM : std_logic_vector(16383 downto 0) :=  INIT_3F &
                                                     INIT_3E &
                                                     INIT_3D &
                                                     INIT_3C &
                                                     INIT_3B &
                                                     INIT_3A &
                                                     INIT_39 &
                                                     INIT_38 &
                                                     INIT_37 &
                                                     INIT_36 &
                                                     INIT_35 &
                                                     INIT_34 &
                                                     INIT_33 &
                                                     INIT_32 &
                                                     INIT_31 &
                                                     INIT_30 &
                                                     INIT_2F &
                                                     INIT_2E &
                                                     INIT_2D &
                                                     INIT_2C &
                                                     INIT_2B &
                                                     INIT_2A &
                                                     INIT_29 &
                                                     INIT_28 &
                                                     INIT_27 &
                                                     INIT_26 &
                                                     INIT_25 &
                                                     INIT_24 &
                                                     INIT_23 &
                                                     INIT_22 &
                                                     INIT_21 &
                                                     INIT_20 &
                                                     INIT_1F &
                                                     INIT_1E &
                                                     INIT_1D &
                                                     INIT_1C &
                                                     INIT_1B &
                                                     INIT_1A &
                                                     INIT_19 &
                                                     INIT_18 &
                                                     INIT_17 &
                                                     INIT_16 &
                                                     INIT_15 &
                                                     INIT_14 &
                                                     INIT_13 &
                                                     INIT_12 &
                                                     INIT_11 &
                                                     INIT_10 &
                                                     INIT_0F &
                                                     INIT_0E &
                                                     INIT_0D &
                                                     INIT_0C &
                                                     INIT_0B &
                                                     INIT_0A &
                                                     INIT_09 &
                                                     INIT_08 &
                                                     INIT_07 &
                                                     INIT_06 &
                                                     INIT_05 &
                                                     INIT_04 &
                                                     INIT_03 &
                                                     INIT_02 &
                                                     INIT_01 &
                                                     INIT_00;

 variable MEMP : std_logic_vector(2047 downto 0) :=  INITP_07 &
                                                     INITP_06 &
                                                     INITP_05 &
                                                     INITP_04 &
                                                     INITP_03 &
                                                     INITP_02 &
                                                     INITP_01 &
                                                     INITP_00;

      begin

       if(WEA = '1') and (ENA = '1') then
            MEM((16*(MEMADDRA+1) -1) downto (16*MEMADDRA)):= DIA;
				MEMP((2*(MEMADDRA+1) -1) downto (2*MEMADDRA)) := DIPA;
       elsif(WEB = '1') and (ENB = '1') then
            MEM((16*(MEMADDRB+1) -1) downto (16*MEMADDRB)):= DIB;
				MEMP((2*(MEMADDRB+1) -1) downto (2*MEMADDRB)) := DIPB;
      end if;

		if rising_edge(CLKA) then
			if(ENA = '1') then
		       DOA <= MEM((16*(MEMADDRA+1) -1) downto (16*MEMADDRA));
		       DOPA <= MEMP((2*(MEMADDRA+1) -1) downto (2*MEMADDRA));
			end if;
		end if;

		if rising_edge(CLKB) then
			if(ENB = '1') then
		       DOB <= MEM((16*(MEMADDRB+1) -1) downto (16*MEMADDRB));
		       DOPB <= MEMP((2*(MEMADDRB+1) -1) downto (2*MEMADDRB));
			end if;
		end if;

end process;

 
END behavior;
