-------------------------------------------------------------
-- MSS copyright 2012-2016
-- Filename:  RECEIVER1.VHD
-- Authors: 
--		Alain Zarembowitch / MSS
-- Version: Rev 5e
-- Last modified: 7/28/16
-- Inheritance: 	N/A
--
-- description:  Front-end digital receiver, including AGC, frequency translation to baseband,
-- variable decimation (cic), one half-band filter for image rejection.
-- Generic: does not depend on modulation.
-- 
-- Rev2: 9/5/12 AZ
-- Provision for smaller input signal (internal gain can be > 1)
--
-- Rev3: 11/3/12 AZ
-- added SAMPLE_CLK_IN input samples enable to include case where samples are not always available.
-- IMPORTANT: the translation frequency is now expressed as a function of the input sampling frequency (not just the 
-- processing clock CLK as before). Special case: when SAMPLE_CLK_IN is constantly set at '1', the translation frequency
-- is expressed as a function of the processing clock frequency fclk, as in previous versions.
-- + added bias removal enable/disable control
-- + added AGC17 enable/disable control and initial AGC gain setting
--
-- Rev 4 2/24/13 AZ
-- Added saturation flag
--
-- Rev 5 4/13/13 AZ
-- Added 4 lsbs to AGC_DAC_local
-- internal AGC is no longer a feedback loop. New gain control algorithm is basically 1/average magnitude.
--
-- Rev 5b 9/30/14 AZ Vivado tools misunderstood the statement (something = 'X') as true
-- had to work around it.
-- 
-- Rev 5c 11/14/14 AZ Move SIMULATION to the generic section
--
-- Rev 5d 7/4/14 AZ
-- For QAM modulation, 16384 samples averaging AGC18 (previously 512) and x8 longer averaging for BIAS_REMOVAL.
--
-- Rev 5e 7/28/16 AZ
-- Upgraded AGC18 (larger dynamic range, faster response)
---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

entity RECEIVER1 is
	generic (
		SIMULATION: std_logic := '0'
			-- 1 during simulation, 0 for release	
	);
    Port ( 
		--// CLK, RESET
		CLK: in std_logic;
			-- demod processing clock and ADC sampling clock from ADC. Must be a global clock (no BUFG within)
			-- Warning: beware of circular logic (CLK is derived from ADC_SAMPLING_CLK_OUT which depends 
			-- on variables synchronous with CLK!)
		SYNC_RESET: in std_logic;
			-- synchronous with CLK
			-- One MUST reset this component after a change in CIC decimation ratio!!! otherwise saturation may occur.

		--// INPUT SAMPLES
		DATA_I_IN: in std_logic_vector(13 downto 0);
		DATA_Q_IN: in std_logic_vector(13 downto 0);
		SAMPLE_CLK_IN: in std_logic;
			-- real or complex input signal. 2's complement signed format
			-- When only a real input is available (IF undersampling configuration), set DATA_Q_IN to zero.
			-- SAMPLE_CLK_IN enable.

		--// AGC OUTPUTS
		AGC_DAC: out std_logic_vector(11 downto 0);
			-- gain control. May need to be inverted depending on the analog front-end.
			-- Here, maximum AGC_DAC really means minimum gain.
		AGC_DAC_SAMPLE_CLK: out std_logic;
			-- read AGC_DAC at the rising edge of CLK when AGC_DAC_SAMPLE_CLK = 1.
		
		--// CONTROLS 
	   AGC_RESPONSE : IN std_logic_vector(4 downto 0);          
			-- Adjust the AGC response time. approximately log2(NSymbols). 
			-- During the preamble, a 4x faster response time is used.
		AGC_INITIAL_GAIN: IN std_logic_vector(11 downto 0); 
			-- initial gain setting for the internal/external AGC. Also fixed gain setting when AGC is disabled.
			-- 12-bit unsigned. FFF represents the minimum gain, 000 the maximum gain.
		CENTER_FREQ: in std_logic_vector(31 downto 0);
			-- nominal (i.e. expected) center frequency. Expressed as fc/demodulator processing clock * 2^32
			-- This frequency is subtracted from the input signal center frequency. 
			-- Add -fclk/4 when used in conjunction with IF undersampling. 
	   CIC_R: in std_logic_vector(15 downto 0);    
			-- CIC Decimation ratio. The output sampling rate is thus fclk/R
			-- 1 to bypass. 0 is illegal, otherwise, nominal range is 1 to 16384.
			-- Usage: be careful not to decimate too much as the CIC decimation filter is not very sharp and thus
			-- can distort the modulated signal. 
			-- Rule of thumb: the CIC filter output sampling rate should be >= 8 samples per symbol.
		
	   CONTROL: in std_logic_vector(2 downto 0);
			-- bit 0: (0) internal AGC enabled, (1) disabled
			-- bit 1: (0) disable , (1) enable external AGC
			-- bit 2: (0) disable , (1) enable bias removal
			-- USAGE: internal AGC can be unstable when used in conjunction with IF undersampling. 
			-- In that case, use external AGC instead or move the internal AGC after HBF or use peak detect within a symbol.

		--// OUTPUT
		DATA_I_OUT: out std_logic_vector(13 downto 0);
		DATA_Q_OUT: out std_logic_vector(13 downto 0);
			-- complex output samples. 2's complement. Read at the rising edge of CLK when SAMPLE_CLK_OUT = '1'.
		SAMPLE_CLK_OUT: out std_logic;
		
		--// TEST POINTS, MONITORING, COMSCOPE TRACES
		SATURATION: out std_logic;
		TP: out std_logic_vector(10 downto 1);
		CS1: out std_logic_vector(7 downto 0);	--TBD
		CS1_CLK: out std_logic;
		CS2: out std_logic_vector(7 downto 0);	-- TBD
		CS2_CLK: out std_logic;
		CS3: out std_logic_vector(7 downto 0);	-- TBD
		CS3_CLK: out std_logic;
		CS4: out std_logic_vector(7 downto 0);	-- TBD
		CS4_CLK: out std_logic

			);
end entity;

architecture Behavioral of RECEIVER1 is
--------------------------------------------------------
--      COMPONENTS
--------------------------------------------------------
	COMPONENT AGC17
	PORT(
		CLK : IN std_logic;
		DATA_M_IN : IN std_logic_vector(13 downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		SYMBOL_CLK_IN : IN std_logic;
		AGC_ENABLE: IN std_logic;
		AGC_INITIAL_GAIN: IN std_logic_vector(11 downto 0); 
		AGC_RESPONSE : IN std_logic_vector(4 downto 0);   
		ACCELERATED_AGC_RESPONSE : IN std_logic;		
		AGC_DAC : OUT std_logic_vector(15 downto 0);
		AGC_DAC_SAMPLE_CLK : OUT std_logic;
		TP : OUT std_logic_vector(10 downto 1);
		CS1 : OUT std_logic_vector(7 downto 0);
		CS1_CLK : OUT std_logic;
		CS2 : OUT std_logic_vector(7 downto 0);
		CS2_CLK : OUT std_logic
		);
	END COMPONENT;

	COMPONENT BIAS_REMOVAL
	 Generic(
		NBITS: integer;
		SIMULATION: std_logic
	 );
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATA_I_IN : IN std_logic_vector((NBITS-1) downto 0);
		DATA_Q_IN : IN std_logic_vector((NBITS-1) downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		SYMBOL_CLK_IN : IN std_logic;
		ENABLE : IN std_logic;          
		DATA_I_OUT : OUT std_logic_vector((NBITS-1) downto 0);
		DATA_Q_OUT : OUT std_logic_vector((NBITS-1) downto 0);
		SAMPLE_CLK_OUT : OUT std_logic
		);
	END COMPONENT;

	COMPONENT AGC18
	 Generic(
		AVERAGING_LENGTH: integer;
		SIMULATION: std_logic
	 );
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATA_I_IN : IN std_logic_vector(13 downto 0);
		DATA_Q_IN : IN std_logic_vector(13 downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		MTARGET : IN std_logic_vector(13 downto 0);
		CONTROL : IN std_logic_vector(0 to 0);
		SYMBOLx2_CLK_IN : IN std_logic;          
		DATA_I_OUT : OUT std_logic_vector(13 downto 0);
		DATA_Q_OUT : OUT std_logic_vector(13 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic;
		SATURATION : OUT std_logic;
		DATA_M : OUT std_logic_vector(13 downto 0);
		SAMPLE_M_CLK : OUT std_logic;
		TP : OUT std_logic_vector(10 downto 1);
		CS1 : OUT std_logic_vector(7 downto 0);
		CS1_CLK : OUT std_logic
		);
	END COMPONENT;

	COMPONENT DIGITAL_DC2
	PORT(
		CLK : IN std_logic;
		DATA_I_IN : IN std_logic_vector(11 downto 0);
		DATA_Q_IN : IN std_logic_vector(11 downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		PHASE_ROTATION : IN std_logic_vector(11 downto 0);          
		DATA_I_OUT : OUT std_logic_vector(11 downto 0);
		DATA_Q_OUT : OUT std_logic_vector(11 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic;
		SATURATION : OUT std_logic
		);
	END COMPONENT;

	COMPONENT CIC
	 Generic(
		N: in integer range 1 to 8;
		M: in integer range 1 to 2;
		SIMULATION: std_logic
	 );
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATA_IN : IN std_logic_vector(11 downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		R : in integer range 1 to 16384;
		TRUNCATE_OBITS : in integer range 0 to 63;         
		DATA_OUT : OUT std_logic_vector(11 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic
		);
	END COMPONENT;

	COMPONENT FIRHALFBAND3
	PORT(
		CLK : IN std_logic;
		SAMPLE_CLK_IN : IN std_logic;
		DATA_IN : IN std_logic_vector(13 downto 0);          
		SAMPLE_CLK_OUT : OUT std_logic;
		DATA_OUT : OUT std_logic_vector(13 downto 0)
		);
	END COMPONENT;

	component SIM2OUTFILE is
		 Generic (
			FILENAME: string
		 );
		 Port ( 
			--// CLK, RESET
			CLK: in std_logic;
				-- Reference clock
			DATA1: in std_logic_vector(11 downto 0);
			DATA2: in std_logic_vector(11 downto 0);
			DATA3: in std_logic_vector(11 downto 0);
			SAMPLE_CLK_IN: in std_logic
				-- DATA_IN is read at the rising edge of CLK when SAMPLE_CLK_IN = '1'

	);
	END COMPONENT;

--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
-- Suffix _D indicates a one CLK delayed version of the net with the same name
-- Suffix _DR indicates rising edge (1st half of the symbol clock)
-- Suffix _DF indicates falling edge (2nd half of the symbol clock)
-- Suffix _X indicates an extended precision version of the net with the same name
-- Suffix _N indicates an inverted version of the net with the same name
-- Suffix _E indicates a one CLK early version of the net with the same name

--//-- STATE MACHINE ------------------------------------------------
signal STATE: integer range 0 to 5 := 0;	-- future

--//-- EXTERNAL AGC --------------------------------------------------------------
signal AGC_DAC_local: std_logic_vector(15 downto 0) := (others => '0');
signal AGC_DAC_SAMPLE_CLK_local: std_logic := '0';
signal ACCELERATED_AGC_RESPONSE: std_logic := '0';


--//-- BIAS REMOVAL ---------------------------------------
signal DATA1_I: std_logic_vector(13 downto 0) := (others => '0');
signal DATA1_Q: std_logic_vector(13 downto 0) := (others => '0');
signal SAMPLE1_CLK: std_logic := '0';
signal BIAS_REMOVAL_RESET: std_logic := '0';

--//-- INTERNAL AGC --------------------------------------------------------------
signal DATA3_I: std_logic_vector(13 downto 0) := (others => '0');
signal DATA3_Q: std_logic_vector(13 downto 0) := (others => '0');
signal SAMPLE3_CLK: std_logic := '0';
signal SATURATION_AGC: std_logic := '0';
signal AGC18_CONTROL: std_logic_vector(0 downto 0) := (others => '0');
signal DATA1M: std_logic_vector(13 downto 0) := (others => '0');
signal SAMPLE1M_CLK: std_logic := '0';

--//-- FREQUENCY TRANSLATION -------------------------------
signal PHASE_ROTATION: std_logic_vector(31 downto 0) := (others => '0');
signal DATA4_I: std_logic_vector(11 downto 0) := (others => '0');
signal DATA4_Q: std_logic_vector(11 downto 0) := (others => '0');
signal SAMPLE4_CLK: std_logic := '0';
signal SATURATION_DC2: std_logic := '0';

--//-- VARIABLE DECIMATION  PART I : CIC DECIMATION  -----------------------
signal CIC_RESET: std_logic := '0';
signal DATA5_I: std_logic_vector(11 downto 0) := (others => '0');
signal DATA5_Q: std_logic_vector(11 downto 0) := (others => '0');
signal DATA5_I_X: std_logic_vector(13 downto 0) := (others => '0');
signal DATA5_Q_X: std_logic_vector(13 downto 0) := (others => '0');
signal SAMPLE5_CLK: std_logic := '0';
signal CIC_TRUNCATE_OBITS: integer range 0 to 63;
		-- decimation filter: number of least significant bits to be truncated at the output. 
		-- Must be set to N*log2(RM), which is the bit growth during the CIC
		-- calculation due to the gain G = (RM)^N.
		-- As this CIC module is designed to be flexible, it is generally more efficient
		-- to compute this field by the application (i.e. outside this module) 
		-- since the parameters N,R,M are generally known and fixed at the time of 
		-- synthesis.
signal CIC_R_BIN_DEC: std_logic_vector(15 downto 0) := (others => '0');
		-- intermediate computation: R-1
signal R: integer range 1 to 16384;

--//-- VARIABLE BANDWIDTH FILTER  PART II: HALF-BAND FILTERS --------------------------
signal DATA6_I: std_logic_vector(13 downto 0) := (others => '0');
signal DATA6_Q: std_logic_vector(13 downto 0) := (others => '0');
signal SAMPLE6_CLK: std_logic := '0';
--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
begin

--//-- STATE MACHINE ------------------------------------------------
STATE <= 2;	-- tracking (no burst mode)


--//-- EXTERNAL AGC --------------------------------------------------------------
ACCELERATED_AGC_RESPONSE <= '1' when (STATE = 0) else '0';
Inst_AGC17: AGC17 PORT MAP(
	CLK => CLK,
	DATA_M_IN => DATA1M,	-- unsigned
	SAMPLE_CLK_IN => SAMPLE1M_CLK,
	SYMBOL_CLK_IN => SAMPLE6_CLK,	
	AGC_ENABLE => CONTROL(1),
	AGC_INITIAL_GAIN => AGC_INITIAL_GAIN,
	AGC_RESPONSE => AGC_RESPONSE,	
	ACCELERATED_AGC_RESPONSE => ACCELERATED_AGC_RESPONSE,
	AGC_DAC => AGC_DAC_local,
	AGC_DAC_SAMPLE_CLK => AGC_DAC_SAMPLE_CLK_local,
	TP => open,
	CS1 => open,
	CS1_CLK => open,
	CS2 => open,
	CS2_CLK => open
);
AGC_DAC <= AGC_DAC_local(15 downto 4);
AGC_DAC_SAMPLE_CLK <= AGC_DAC_SAMPLE_CLK_local;


--//-- BIAS REMOVAL ---------------------------------------
-- Bias removal. Make the signal symmetrical around zero. 

BIAS_REMOVAL_RESET <= '1' when (STATE = 0) else '0';

-- 1 CLK latency
BIAS_REMOVAL_001: BIAS_REMOVAL 
GENERIC MAP(
	NBITS => 14,
	SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK,
	SYNC_RESET => BIAS_REMOVAL_RESET,
	DATA_I_IN => DATA_I_IN,
	DATA_Q_IN => DATA_Q_IN,
	SAMPLE_CLK_IN => SAMPLE_CLK_IN,
	SYMBOL_CLK_IN => SAMPLE6_CLK,
	ENABLE => CONTROL(2),
	DATA_I_OUT => DATA1_I,
	DATA_Q_OUT => DATA1_Q,
	SAMPLE_CLK_OUT => SAMPLE1_CLK
);

--//-- INTERNAL AGC --------------------------------------------------------------
-- Feedforward gain control: input is scaled by 1/average magnitude

AGC18_CONTROL(0) <= not CONTROL(0);		-- '1' when internal AGC, '0' when bypassed (unit gain)
AGC18_001: AGC18 
GENERIC MAP(
--	AVERAGING_LENGTH => 16384,	-- QAM. could be reduced in the case of constant-amplitude modulation
	AVERAGING_LENGTH => 512,
	SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK,
	SYNC_RESET => SYNC_RESET,
	DATA_I_IN => DATA1_I,
	DATA_Q_IN => DATA1_Q,
	SAMPLE_CLK_IN => SAMPLE1_CLK,
	MTARGET => "00110000000000",
	CONTROL => AGC18_CONTROL,
	SYMBOLx2_CLK_IN => SAMPLE6_CLK,
	DATA_I_OUT => DATA3_I,
	DATA_Q_OUT => DATA3_Q,
	SAMPLE_CLK_OUT => SAMPLE3_CLK,
	SATURATION => SATURATION_AGC,
	DATA_M => DATA1M,
	SAMPLE_M_CLK => SAMPLE1M_CLK,
	TP => open,
	CS1 => open,
	CS1_CLK => open
);


--//-- FREQUENCY TRANSLATION -------------------------------
-- Remove center frequency. 
-- latency 3 CLKs
DIGITAL_DC_001: DIGITAL_DC2 PORT MAP(
	CLK => CLK,
	DATA_I_IN => DATA3_I(13 downto 2),
	DATA_Q_IN => DATA3_Q(13 downto 2),
	SAMPLE_CLK_IN => SAMPLE3_CLK,
	PHASE_ROTATION => PHASE_ROTATION(31 downto 20),
	DATA_I_OUT => DATA4_I,	
	DATA_Q_OUT => DATA4_Q,
	SAMPLE_CLK_OUT => SAMPLE4_CLK,
	SATURATION => SATURATION_DC2
);


-- NCO corrects for fixed offset as set by user in CENTER_FREQ 
-- remove center frequency
NCO_001: process (CLK)
begin 
	if rising_edge(CLK) then
		if(SYNC_RESET = '1') then
			PHASE_ROTATION <= (others => '0');
--			PHASE_ROTATION <= x"F0000000";	-- for simulation purposes (careful: affects all instances if multiple instantiations)
--		elsif((SIMULATION = '0') or (CENTER_FREQ(31) /= 'X')) and (SAMPLE3_CLK = '1') then
-- HERE frequency offset is expressed as a function of the processing clock, not sampling rate
-- 10/15/14
		elsif((SIMULATION = '0') or (CENTER_FREQ(31) /= 'X')) then
			PHASE_ROTATION <= PHASE_ROTATION - CENTER_FREQ;
		end if;
	end if;
end process;


--// VARIABLE BANDWIDTH FILTER  PART I : CIC FILTER  -----------------------
-- Use CIC filters to reject far-out, half-band filter to reject close to the target bandwidth = best of breeds.
-- Two filters, one each for I and Q.
-- The decimation rate R must be selected such that fclk/R is strictly greater than
-- 4* symbol rate. 
CIC_R_BIN_DEC <= CIC_R -1;

-- compute the number of bits to truncate: 
-- reclock for best timing. Update only at reset.
CIC_TRUNCATE_OBITS_GEN: process(CLK, CIC_R_BIN_DEC)
begin
	if rising_edge(CLK) then
		CIC_RESET <= SYNC_RESET;
		
		if(SYNC_RESET = '1') then
			if(CIC_R_BIN_DEC(15) = '1') then
				CIC_TRUNCATE_OBITS <= 32;
			elsif(CIC_R_BIN_DEC(14) = '1') then
				CIC_TRUNCATE_OBITS <= 30;
			elsif(CIC_R_BIN_DEC(13) = '1') then
				CIC_TRUNCATE_OBITS <= 28;
			elsif(CIC_R_BIN_DEC(12) = '1') then
				CIC_TRUNCATE_OBITS <= 26;
			elsif(CIC_R_BIN_DEC(11) = '1') then
				CIC_TRUNCATE_OBITS <= 24;
			elsif(CIC_R_BIN_DEC(10) = '1') then
				CIC_TRUNCATE_OBITS <= 22;
			elsif(CIC_R_BIN_DEC(9) = '1') then
				CIC_TRUNCATE_OBITS <= 20;
			elsif(CIC_R_BIN_DEC(8) = '1') then
				CIC_TRUNCATE_OBITS <= 18;
			elsif(CIC_R_BIN_DEC(7) = '1') then
				CIC_TRUNCATE_OBITS <= 16;
			elsif(CIC_R_BIN_DEC(6) = '1') then
				CIC_TRUNCATE_OBITS <= 14;
			elsif(CIC_R_BIN_DEC(5) = '1') then
				CIC_TRUNCATE_OBITS <= 12;
			elsif(CIC_R_BIN_DEC(4) = '1') then
				CIC_TRUNCATE_OBITS <= 10;
			elsif(CIC_R_BIN_DEC(3) = '1') then
				CIC_TRUNCATE_OBITS <= 8;
			elsif(CIC_R_BIN_DEC(2) = '1') then
				CIC_TRUNCATE_OBITS <= 6;
			elsif(CIC_R_BIN_DEC(1) = '1') then
				CIC_TRUNCATE_OBITS <= 4;
			elsif(CIC_R_BIN_DEC(0) = '1') then
				CIC_TRUNCATE_OBITS <= 2;
			else
				CIC_TRUNCATE_OBITS <= 0;
			end if;
		end if;
	end if;
end process;

R <= conv_integer(CIC_R);

CIC_FILTER_001: CIC 
GENERIC MAP(
	N => 2,
	M => 1,
	SIMULATION => SIMULATION
)
port map(
	CLK => CLK,
	SYNC_RESET => CIC_RESET, -- CIC must be reset upon changing decimation ratio, otherwise saturation will occur.
	DATA_IN => DATA4_I,
	SAMPLE_CLK_IN => SAMPLE4_CLK,	
	R => R,
	TRUNCATE_OBITS => CIC_TRUNCATE_OBITS,
	DATA_OUT => DATA5_I,
	SAMPLE_CLK_OUT => SAMPLE5_CLK
	);

CIC_FILTER_002: CIC 
GENERIC MAP(
	N => 2,
	M => 1,
	SIMULATION => SIMULATION
)
port map(
	CLK => CLK,
	SYNC_RESET => CIC_RESET,
	DATA_IN => DATA4_Q,
	SAMPLE_CLK_IN => SAMPLE4_CLK,	
	R => R,
	TRUNCATE_OBITS => CIC_TRUNCATE_OBITS,
	DATA_OUT => DATA5_Q,
	SAMPLE_CLK_OUT => open
	);

--//-- VARIABLE BANDWIDTH FILTER  PART II: HALF-BAND FILTERS --------------------------
-- latency 6 CLK
DATA5_I_X <= DATA5_I & "00";
DATA5_Q_X <= DATA5_Q & "00";

FIRHALFBAND3_I1: FIRHALFBAND3 PORT MAP(
	CLK => CLK,
	SAMPLE_CLK_IN => SAMPLE5_CLK,		
	DATA_IN => DATA5_I_X,
	SAMPLE_CLK_OUT => SAMPLE6_CLK,		
	DATA_OUT => DATA6_I
);

FIRHALFBAND3_Q1: FIRHALFBAND3 PORT MAP(
	CLK => CLK,
	SAMPLE_CLK_IN => SAMPLE5_CLK,		
	DATA_IN => DATA5_Q_X,
	SAMPLE_CLK_OUT => open,		
	DATA_OUT => DATA6_Q
);

--// OUTPUT ----------------------------------
DATA_I_OUT <= DATA6_I;
DATA_Q_OUT <= DATA6_Q;
SAMPLE_CLK_OUT <= SAMPLE6_CLK;
SATURATION_OUT: process(CLK)
begin
	if rising_edge(CLK) then
		SATURATION <= SATURATION_AGC or SATURATION_DC2;
	end if;
end process;


--// TEST POINTS, MONITORING ----------------------------------
--TP(1) <= ;

-- comscope traces
CS1 <= DATA1M(12 downto 5);
CS1_CLK <= SAMPLE1M_CLK;
CS2 <= DATA1_I(13 downto 6);
CS2_CLK <= SAMPLE1_CLK;
CS3 <= DATA3_I(13 downto 6);
CS3_CLK <= SAMPLE3_CLK;
CS4 <= DATA4_I(11 downto 4);
CS4_CLK <= SAMPLE4_CLK;

--// simulation. send to a tab-delimited text file for subsequent (Matlab) plot.
SIM2OUTFILE_X: if(SIMULATION = '1') generate
--	Inst_SIM2OUTFILE1: SIM2OUTFILE 
--	generic map(
--		FILENAME => "r1.txt"
--	)
--	PORT MAP(
--		CLK => CLK,
--		DATA1 => DATA_I_IN(13 downto 2),
--		DATA2 => DATA_Q_IN(13 downto 2),
--		DATA3 => DATA1_I(13 downto 2),	
--		SAMPLE_CLK_IN => SAMPLE_CLK_IN
--	);
--
--
--
--	Inst_SIM2OUTFILE4: SIM2OUTFILE 
--	generic map(
--		FILENAME => "r4.txt"
--	)
--	PORT MAP(
--		CLK => CLK,
--		DATA1 => DATA1_I(13 downto 2),	
--		DATA2 => DATA1_Q(13 downto 2),	
--		DATA3 => DATA3_I(13 downto 2),	
--		SAMPLE_CLK_IN => SAMPLE1_CLK
--	);
--
--	Inst_SIM2OUTFILE5: SIM2OUTFILE 
--	generic map(
--		FILENAME => "r5.txt"
--	)
--	PORT MAP(
--		CLK => CLK,
--		DATA1 => DATA3_I(13 downto 2),
--		DATA2 => DATA3_Q(13 downto 2),
--		DATA3 => DATA4_I,
--		SAMPLE_CLK_IN => SAMPLE3_CLK
--	);
end generate;


end Behavioral;

