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-- MSS copyright 1999-2000
-- VHDL code for generic adders
-- Primary project: channel unit v3
-- Author: Alain Zarembowitch / MSS
-- Edit date: 7-27-00
-- Revision: 3
-- 16-bit adder
--
-- Changes in Rev 3:
--		replaced previous version (Carry ahead rev1, Xilinx Macro rev2)
--		with generic VHDL code as synthesis tools are good enough to synthesize this high level statement
----------------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity fcadd16_2 is
	port (
		ci: 	in std_logic;
		a15,a14,a13,a12,a11,a10,a9,a8,a7,a6,a5,a4,a3,a2,a1,a0:	in std_logic;
		b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0:	in std_logic;
		sum15,sum14,sum13,sum12,sum11,sum10,sum9,sum8,sum7,sum6,sum5,sum4,sum3,sum2,sum1,sum0: out std_logic;
		co: out std_logic);
end fcadd16_2;

architecture archfcadd16_2 of fcadd16_2 is

signal summer, ain, bin: std_logic_vector(16 downto 0);   
signal cin: std_logic_vector(16 downto 0);

begin

-- for simulation purposes
cin(16 downto 1) <= (others => '0');
cin(0) <= ci;
summer <= ain + bin + cin;
--summer <= ain + bin + ci;

ain(0) <=a0;
ain(1) <=a1;
ain(2) <=a2;
ain(3) <=a3;
ain(4) <=a4;
ain(5) <=a5;
ain(6) <=a6;
ain(7) <=a7;
ain(8) <=a8;
ain(9) <=a9;
ain(10) <=a10;
ain(11) <=a11;
ain(12) <=a12;
ain(13) <=a13;
ain(14) <=a14;
ain(15) <=a15;
ain(16) <='0';

bin(0) <= b0;
bin(1) <= b1;
bin(2) <= b2;
bin(3) <= b3;
bin(4) <= b4;
bin(5) <= b5;
bin(6) <= b6;
bin(7) <= b7;
bin(8) <= b8;
bin(9) <= b9;
bin(10) <= b10;
bin(11) <= b11;
bin(12) <= b12;
bin(13) <= b13;
bin(14) <= b14;
bin(15) <= b15;
bin(16) <= '0';
sum0 <= summer(0);
sum1 <= summer(1);
sum2 <= summer(2);
sum3 <= summer(3);
sum4 <= summer(4);
sum5 <= summer(5);
sum6 <= summer(6);
sum7 <= summer(7);
sum8 <= summer(8);
sum9 <= summer(9);
sum10 <= summer(10);
sum11 <= summer(11);
sum12 <= summer(12);
sum13 <= summer(13);
sum14 <= summer(14);
sum15 <= summer(15);

co <= summer(16);

end archfcadd16_2;

