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-- Company: 
-- Engineer:
--
-- Create Date:   11:33:34 01/04/2010
-- Design Name:   
-- Module Name:   C:/Users/Admin/Documents/VHDL source/firrcos20/simul/tbfirrcos20.vhd
-- Project Name:  firrcos20
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: firrcos20
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tbfirrcos20 IS
END tbfirrcos20;
 
ARCHITECTURE behavior OF tbfirrcos20 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT firrcos20
    PORT(
         CLK : IN  std_logic;
         SAMPLE_CLK_IN : IN  std_logic;
         DATA_IN : IN  std_logic_vector(13 downto 0);
         SAMPLE_CLK_OUT : OUT  std_logic;
         DATA_OUT : OUT  std_logic_vector(13 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal SAMPLE_CLK_IN : std_logic := '0';
   signal DATA_IN : std_logic_vector(13 downto 0) := (others => '0');

 	--Outputs
   signal SAMPLE_CLK_OUT : std_logic;
   signal DATA_OUT : std_logic_vector(13 downto 0);
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: firrcos20 PORT MAP (
          CLK => CLK,
          SAMPLE_CLK_IN => SAMPLE_CLK_IN,
          DATA_IN => DATA_IN,
          SAMPLE_CLK_OUT => SAMPLE_CLK_OUT,
          DATA_OUT => DATA_OUT
        );
 
  
   CLK_process :process
   begin
		CLK <= '0';
		wait for 5ns;
		CLK <= '1';
		wait for 5ns;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
		SAMPLE_CLK_IN <= '0';
		wait for 90 ns;
		SAMPLE_CLK_IN <= '1';
		wait for 10 ns;
   end process;

   stim_proc2: process
   begin		
		DATA_IN <= (others => '0');
		wait for 2090 ns;
		DATA_IN <= "01111111111111";
		wait for 10 ns;
		DATA_IN <= (others => '0');
      wait;
   end process;

END;
