--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   11:05:57 10/22/2014
-- Design Name:   
-- Module Name:   C:/Users/Alain/Documents/source_VHDL/com-7003_000/src/arith/tb_arith.vhd
-- Project Name:  com-7003
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ARITH
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb_arith IS
END tb_arith;
 
ARCHITECTURE behavior OF tb_arith IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ARITH
    PORT(
         CLK : IN  std_logic;
         SYNC_RESET : IN  std_logic;
         OPERAND_A : IN  std_logic_vector(17 downto 0);
         OPERAND_A_VALID : IN  std_logic;
         OPERAND_B : IN  std_logic_vector(17 downto 0);
         OPERAND_B_VALID : IN  std_logic;
         OP : IN  std_logic_vector(3 downto 0);
         OP_VALID : IN  std_logic;
         RESULT : OUT  std_logic_vector(35 downto 0);
         RESULT_VALID : OUT  std_logic;
         READY : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal SYNC_RESET : std_logic := '0';
   signal OPERAND_A : std_logic_vector(17 downto 0) := (others => '0');
   signal OPERAND_A_VALID : std_logic := '0';
   signal OPERAND_B : std_logic_vector(17 downto 0) := (others => '0');
   signal OPERAND_B_VALID : std_logic := '0';
   signal OP : std_logic_vector(3 downto 0) := (others => '0');
   signal OP_VALID : std_logic := '0';

 	--Outputs
   signal RESULT : std_logic_vector(35 downto 0);
	signal RESULT_VALID: std_logic;
   signal READY : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ARITH PORT MAP (
          CLK => CLK,
          SYNC_RESET => SYNC_RESET,
          OPERAND_A => OPERAND_A,
          OPERAND_A_VALID => OPERAND_A_VALID,
          OPERAND_B => OPERAND_B,
          OPERAND_B_VALID => OPERAND_B_VALID,
          OP => OP,
          OP_VALID => OP_VALID,
          RESULT => RESULT,
			 RESULT_VALID => RESULT_VALID,
          READY => READY
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
		OP_VALID <= '0';
		wait for 500 ns;
		OPERAND_A <= "00" & x"1000";
		OPERAND_B <= "00" & x"1000";
		OPERAND_A_VALID <= '0';
		OPERAND_B_VALID <= '0';
		OP <= "0001";
		OPERAND_A_VALID <= '1';
		OPERAND_B_VALID <= '1';
		OP_VALID <= '1';
		wait for 10 ns;
		OPERAND_A_VALID <= '0';
		OPERAND_B_VALID <= '0';
		OP_VALID <= '0';
		wait for 500 ns;
		OPERAND_A <= "00" & x"0021";
		OPERAND_B <= "00" & x"0000";
		OPERAND_A_VALID <= '0';
		OPERAND_B_VALID <= '0';
		OP <= "0101";
		OPERAND_A_VALID <= '1';
		OPERAND_B_VALID <= '1';
		OP_VALID <= '1';
		wait for 10 ns;
		OPERAND_A_VALID <= '0';
		OPERAND_B_VALID <= '0';
		OP_VALID <= '0';
      wait;
   end process;

END;
