----------------------------------------------
-- MSS copyright 1999-2006
-- Filename: RAISED_COS5E
-- Author: Adam Kwiatkowski / MSS
-- Inheritance: RAISED_COS5D.VHD, rev 0, 9-8-05
-- Edit date: 1/29/06
-- Revision: 2 
--
-- VHDL code for single raised cosine square root FIR. No decimation.
-- 40% rolloff. Single stream. 
-- Input: 4 samples / symbol
-- Output: 4 samples / symbol
-- Maximum rate: one input sample per CLK.
-- Latency is 5 CLK.
--
-- FPGA Performance Statistics (3s1500fg676-4)
--Logic Utilization:
--  Number of Slice Flip Flops: 		639        
--  Number of 4 input LUTs:             555
--
--Timing Summary:
---------------
--Speed Grade: -4		  
-- Minimum period: 10.125ns (Maximum Frequency: 98.765MHz)
-- Minimum input arrival time before clock: 3.941ns
-- Maximum output required time after clock: 5.835ns
--
-- Rev 1  9/16/05 AZ
-- Restored another layer of pipelining for timing reasons.
-- Also makes latency the same for all root raised cosine filters (5 CLKs).
--
-- Rev 2 1/29/06 AZ
-- corrected bug in final clamping.
----------------------------------------------      
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity RAISED_COS5E is
    port (
		CLK: in std_logic;
			-- reference clock for synchronous design
        	-- Input to Output Processing latency 5 CLK periods.
		SAMPLE_CLK_IN: in std_logic;
			-- read input sample at rising_edge of CLK and SAMPLE_CLK_IN  = '1'.
			-- One CLK wide pulse.
		DATA_IN: in std_logic_vector(13 downto 0);
			-- input signal
			-- read at rising edge of CLK when SAMPLE_CLK_IN = '1'

		SAMPLE_CLK_OUT: out std_logic;
		DATA_OUT: out std_logic_vector(13 downto 0)
			-- signal after raised cosine square root filter.
			-- Read at rising edge of CLK and SAMPLE_CLK_OUT = '1'.
    );
end RAISED_COS5E;

architecture behavior  of RAISED_COS5E is
-----------------------------------------------------------------
-- COMPONENTS
-----------------------------------------------------------------
-----------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------
-- suffix _D denotes a one-CLK delayed version of the net with the same name

-- Filter input
signal FIL_IN0: std_logic_vector(13 downto 0);
signal FIL_IN1: std_logic_vector(13 downto 0);
signal FIL_IN2: std_logic_vector(13 downto 0);
signal FIL_IN3: std_logic_vector(13 downto 0);
signal FIL_IN4: std_logic_vector(13 downto 0);
signal FIL_IN5: std_logic_vector(13 downto 0);
signal FIL_IN6: std_logic_vector(13 downto 0);
signal FIL_IN7: std_logic_vector(13 downto 0);
signal FIL_IN8: std_logic_vector(13 downto 0);
signal FIL_IN9: std_logic_vector(13 downto 0);
signal FIL_IN10: std_logic_vector(13 downto 0);
signal FIL_IN11: std_logic_vector(13 downto 0);
signal FIL_IN12: std_logic_vector(13 downto 0);
signal FIL_IN13: std_logic_vector(13 downto 0);
signal FIL_IN14: std_logic_vector(13 downto 0);
signal FIL_IN15: std_logic_vector(13 downto 0);
signal FIL_IN16: std_logic_vector(13 downto 0);
signal FIL_IN17: std_logic_vector(13 downto 0);
signal FIL_IN18: std_logic_vector(13 downto 0);
signal FIL_IN19: std_logic_vector(13 downto 0);
signal FIL_IN20: std_logic_vector(13 downto 0);
signal FIL_IN21: std_logic_vector(13 downto 0);
signal FIL_IN22: std_logic_vector(13 downto 0);
signal FIL_IN23: std_logic_vector(13 downto 0);
signal FIL_IN24: std_logic_vector(13 downto 0);
signal FIL_IN25: std_logic_vector(13 downto 0);
signal FIL_IN26: std_logic_vector(13 downto 0);
signal FIL_IN27: std_logic_vector(13 downto 0);
signal FIL_IN28: std_logic_vector(13 downto 0); 
signal FIL_IN29: std_logic_vector(13 downto 0); 
signal FIL_IN30: std_logic_vector(13 downto 0); 
signal FIL_IN31: std_logic_vector(13 downto 0); 

-- temporary nets
signal FIL_A1: std_logic_vector(8 downto 0);
signal FIL_A2: std_logic_vector(8 downto 0);
signal FIL_A: std_logic_vector(8 downto 0);
signal FIL_A_D: std_logic_vector(8 downto 0);
signal FIL_B1: std_logic_vector(9 downto 0);
signal FIL_B2: std_logic_vector(9 downto 0);
signal FIL_B: std_logic_vector(9 downto 0);
signal FIL_C1: std_logic_vector(7 downto 0);
signal FIL_C2: std_logic_vector(7 downto 0);
signal FIL_C: std_logic_vector(7 downto 0);
signal FIL_D1: std_logic_vector(9 downto 0);
signal FIL_D2: std_logic_vector(9 downto 0);
signal FIL_D: std_logic_vector(9 downto 0);
signal FIL_E1: std_logic_vector(9 downto 0);
signal FIL_E2: std_logic_vector(9 downto 0);
signal FIL_E: std_logic_vector(9 downto 0);
signal FIL_F1: std_logic_vector(8 downto 0);
signal FIL_F2: std_logic_vector(8 downto 0);
signal FIL_F: std_logic_vector(8 downto 0);
signal FIL_G1: std_logic_vector(10 downto 0);
signal FIL_G2: std_logic_vector(10 downto 0);
signal FIL_G: std_logic_vector(10 downto 0);
signal FIL_H1: std_logic_vector(11 downto 0);
signal FIL_H2: std_logic_vector(11 downto 0);
signal FIL_H: std_logic_vector(11 downto 0);
signal FIL_I1: std_logic_vector(8 downto 0);
signal FIL_I2: std_logic_vector(8 downto 0);
signal FIL_I: std_logic_vector(8 downto 0);
signal FIL_J1: std_logic_vector(12 downto 0);
signal FIL_J2: std_logic_vector(12 downto 0);
signal FIL_J: std_logic_vector(12 downto 0);
signal FIL_K1: std_logic_vector(12 downto 0);
signal FIL_K2: std_logic_vector(12 downto 0);
signal FIL_K: std_logic_vector(12 downto 0);
signal FIL_L1: std_logic_vector(11 downto 0);
signal FIL_L2: std_logic_vector(11 downto 0);
signal FIL_L: std_logic_vector(11 downto 0);
signal FIL_M1: std_logic_vector(12 downto 0);
signal FIL_M2: std_logic_vector(12 downto 0);
signal FIL_M: std_logic_vector(12 downto 0);
signal FIL_NA1: std_logic_vector(14 downto 0);
signal FIL_NA2: std_logic_vector(14 downto 0);
signal FIL_NA: std_logic_vector(14 downto 0);
signal FIL_NB1: std_logic_vector(15 downto 0);
signal FIL_NB2: std_logic_vector(15 downto 0);
signal FIL_NB: std_logic_vector(15 downto 0);

signal FIL_O1: std_logic_vector(9 downto 0);
signal FIL_O2: std_logic_vector(9 downto 0);
signal FIL_O: std_logic_vector(9 downto 0);
signal FIL_O_D: std_logic_vector(9 downto 0);
signal FIL_P1: std_logic_vector(10 downto 0);
signal FIL_P2: std_logic_vector(10 downto 0);
signal FIL_P: std_logic_vector(10 downto 0);
signal FIL_P_D: std_logic_vector(10 downto 0);
signal FIL_Q1: std_logic_vector(8 downto 0);
signal FIL_Q2: std_logic_vector(8 downto 0);
signal FIL_Q: std_logic_vector(8 downto 0);
signal FIL_Q_D: std_logic_vector(8 downto 0);
signal FIL_R1: std_logic_vector(10 downto 0);
signal FIL_R2: std_logic_vector(10 downto 0);
signal FIL_R: std_logic_vector(10 downto 0);
signal FIL_R_D: std_logic_vector(10 downto 0);
signal FIL_S1: std_logic_vector(11 downto 0);
signal FIL_S2: std_logic_vector(11 downto 0);
signal FIL_S: std_logic_vector(11 downto 0);
signal FIL_S_D: std_logic_vector(11 downto 0);
signal FIL_T1: std_logic_vector(12 downto 0);
signal FIL_T2: std_logic_vector(12 downto 0);
signal FIL_T: std_logic_vector(12 downto 0);
signal FIL_T_D: std_logic_vector(12 downto 0);
signal FIL_U1: std_logic_vector(9 downto 0);
signal FIL_U2: std_logic_vector(9 downto 0);
signal FIL_U: std_logic_vector(9 downto 0);
signal FIL_U_D: std_logic_vector(9 downto 0);
signal FIL_V1: std_logic_vector(9 downto 0);
signal FIL_V2: std_logic_vector(9 downto 0);
signal FIL_V: std_logic_vector(9 downto 0);
signal FIL_V_D: std_logic_vector(9 downto 0);
signal FIL_W1: std_logic_vector(12 downto 0);
signal FIL_W2: std_logic_vector(12 downto 0);
signal FIL_W: std_logic_vector(12 downto 0);
signal FIL_W_D: std_logic_vector(12 downto 0);
signal FIL_X1: std_logic_vector(13 downto 0);
signal FIL_X2: std_logic_vector(13 downto 0);
signal FIL_X: std_logic_vector(13 downto 0);
signal FIL_X_D: std_logic_vector(13 downto 0);
signal FIL_XA1: std_logic_vector(9 downto 0);
signal FIL_XA2: std_logic_vector(9 downto 0);
signal FIL_XA: std_logic_vector(9 downto 0);
signal FIL_XA_D: std_logic_vector(9 downto 0);
signal FIL_XB1: std_logic_vector(13 downto 0);
signal FIL_XB2: std_logic_vector(13 downto 0);
signal FIL_XB: std_logic_vector(13 downto 0);
signal FIL_XB_D: std_logic_vector(13 downto 0);
signal FIL_XC1: std_logic_vector(12 downto 0);
signal FIL_XC2: std_logic_vector(12 downto 0);
signal FIL_XC: std_logic_vector(12 downto 0);
signal FIL_XC_D: std_logic_vector(12 downto 0);
signal FIL_XD1: std_logic_vector(15 downto 0);
signal FIL_XD2: std_logic_vector(15 downto 0);
signal FIL_XD: std_logic_vector(15 downto 0);
signal FIL_XD_D: std_logic_vector(15 downto 0);
signal FIL_XE1: std_logic_vector(11 downto 0);
signal FIL_XE2: std_logic_vector(11 downto 0);
signal FIL_XE: std_logic_vector(11 downto 0);
signal FIL_XE_D: std_logic_vector(11 downto 0);
signal FIL_XF1: std_logic_vector(11 downto 0);
signal FIL_XF2: std_logic_vector(11 downto 0);
signal FIL_XF: std_logic_vector(11 downto 0);
signal FIL_XG1: std_logic_vector(16 downto 0);
signal FIL_XG2: std_logic_vector(16 downto 0);
signal FIL_XG: std_logic_vector(16 downto 0);
signal FIL_XG_D: std_logic_vector(16 downto 0);
signal FIL_XH1: std_logic_vector(16 downto 0);
signal FIL_XH2: std_logic_vector(16 downto 0);
signal FIL_XH: std_logic_vector(16 downto 0);
signal FIL_IN15_D: std_logic_vector(10 downto 0);


	
signal FIL_Y1: std_logic_vector(11 downto 0);
signal FIL_Y2: std_logic_vector(11 downto 0);
signal FIL_Y: std_logic_vector(11 downto 0);
signal FIL_Z1: std_logic_vector(10 downto 0);
signal FIL_Z2: std_logic_vector(10 downto 0);
signal FIL_Z: std_logic_vector(10 downto 0);
signal FIL_AA1: std_logic_vector(13 downto 0);
signal FIL_AA2: std_logic_vector(13 downto 0);
signal FIL_AA: std_logic_vector(13 downto 0);
signal FIL_BB1: std_logic_vector(12 downto 0);
signal FIL_BB2: std_logic_vector(12 downto 0);
signal FIL_BB: std_logic_vector(12 downto 0);
signal FIL_CC1: std_logic_vector(11 downto 0);
signal FIL_CC2: std_logic_vector(11 downto 0);
signal FIL_CC: std_logic_vector(11 downto 0);
signal FIL_DDA1: std_logic_vector(14 downto 0);
signal FIL_DDA2: std_logic_vector(14 downto 0);
signal FIL_DDA: std_logic_vector(14 downto 0);
signal FIL_DDC1: std_logic_vector(17 downto 0);
signal FIL_DDC2: std_logic_vector(17 downto 0);
signal FIL_DDC: std_logic_vector(17 downto 0);


signal FIL_EE1: std_logic_vector(12 downto 0);
signal FIL_EE2: std_logic_vector(12 downto 0);
signal FIL_EE: std_logic_vector(12 downto 0);
signal FIL_EE_D: std_logic_vector(12 downto 0);
signal FIL_FF1: std_logic_vector(11 downto 0);
signal FIL_FF2: std_logic_vector(11 downto 0);
signal FIL_FF: std_logic_vector(11 downto 0);
signal FIL_FF_D: std_logic_vector(11 downto 0);
signal FIL_GG1: std_logic_vector(13 downto 0);
signal FIL_GG2: std_logic_vector(13 downto 0);
signal FIL_GGA1: std_logic_vector(14 downto 0);
signal FIL_GGA2: std_logic_vector(14 downto 0);
signal FIL_GGA: std_logic_vector(14 downto 0);
signal FIL_GGA_D: std_logic_vector(14 downto 0);
signal FIL_GGB1: std_logic_vector(18 downto 0);
signal FIL_GGB2: std_logic_vector(18 downto 0);
signal FIL_GGB: std_logic_vector(18 downto 0);
signal FIL_GGB_D: std_logic_vector(18 downto 0);
		  
signal FIL_HH1: std_logic_vector(13 downto 0);
signal FIL_HH2: std_logic_vector(13 downto 0);
signal FIL_HH: std_logic_vector(13 downto 0);
signal FIL_HH_D: std_logic_vector(13 downto 0);
signal FIL_HHA1: std_logic_vector(19 downto 0);
signal FIL_HHA2: std_logic_vector(19 downto 0);
signal FIL_HHA: std_logic_vector(19 downto 0);
signal FIL_HHA_D: std_logic_vector(19 downto 0);

signal FIL_II1: std_logic_vector(20 downto 0);
signal FIL_II2: std_logic_vector(20 downto 0);
signal FIL_II3: std_logic_vector(20 downto 0);
signal FIL_II: std_logic_vector(20 downto 0);
		
signal FIL_LL: std_logic_vector(13 downto 0);


signal SAMPLE_CLK_IN_D: std_logic;
signal SAMPLE_CLK_IN_D2: std_logic;
signal SAMPLE_CLK_IN_D3: std_logic;
signal SAMPLE_CLK_IN_D4: std_logic;

-----------------------------------------------------------------
-- IMPLEMENTATION
-----------------------------------------------------------------
begin   

SHIFT_001: process(CLK)
begin
	if(rising_edge(CLK)) then
		if(SAMPLE_CLK_IN = '1') then		
			FIL_IN0 <= DATA_IN;                                                
			FIL_IN1 <= FIL_IN0;                                                
			FIL_IN2 <= FIL_IN1;                                                
			FIL_IN3 <= FIL_IN2;                                                
			FIL_IN4 <= FIL_IN3;                                                
			FIL_IN5 <= FIL_IN4;                                                
			FIL_IN6 <= FIL_IN5;                                                
			FIL_IN7 <= FIL_IN6;                                                
			FIL_IN8 <= FIL_IN7;                                                
			FIL_IN9 <= FIL_IN8;                                                
			FIL_IN10 <= FIL_IN9;                                                
			FIL_IN11 <= FIL_IN10;                                                
			FIL_IN12 <= FIL_IN11;                                                
			FIL_IN13 <= FIL_IN12;                                                
			FIL_IN14 <= FIL_IN13;                                                
			FIL_IN15 <= FIL_IN14;                                                
			FIL_IN16 <= FIL_IN15;
			FIL_IN17 <= FIL_IN16;                                                
			FIL_IN18 <= FIL_IN17;                                                
			FIL_IN19 <= FIL_IN18;                                                
			FIL_IN20 <= FIL_IN19;                                                
			FIL_IN21 <= FIL_IN20;                                                
			FIL_IN22 <= FIL_IN21;                                                
			FIL_IN23 <= FIL_IN22;                                                
			FIL_IN24 <= FIL_IN23;                                                
			FIL_IN25 <= FIL_IN24;                                                
			FIL_IN26 <= FIL_IN25;                                                
			FIL_IN27 <= FIL_IN26;                                                
			FIL_IN28 <= FIL_IN27; 
			FIL_IN29 <= FIL_IN28; 
			FIL_IN30 <= FIL_IN29; 
			FIL_IN31 <= FIL_IN30; 
		end if;
	end if;
end process;


-- FIRST LEVEL OF ADDERS (fold)
-- coeff(1) = coeff(31) = 16/8192 
FIL_A1 <= FIL_IN0(13) & FIL_IN0(13 downto 6);
FIL_A2 <= FIL_IN30(13) & FIL_IN30(13 downto 6);
FIL_A <= FIL_A1 + FIL_A2;

-- coeff(2) = coeff(30) = 32/8192
FIL_B1 <= FIL_IN1(13) & FIL_IN1(13 downto 5);
FIL_B2 <= FIL_IN29(13) & FIL_IN29(13 downto 5);
FIL_B <= FIL_B1 + FIL_B2;

-- coeff(3) = coeff(29) = 8/8192 
FIL_C1 <= FIL_IN2(13) & FIL_IN2(13 downto 7);
FIL_C2 <= FIL_IN28(13) & FIL_IN28(13 downto 7);
FIL_C <= FIL_C1 + FIL_C2;

-- coeff(4) = coeff(28) = -32/8192 
-- subtraction (negative sign) done at upper levels
FIL_D1 <= FIL_IN3(13) & FIL_IN3(13 downto 5);
FIL_D2 <= FIL_IN27(13) & FIL_IN27(13 downto 5);
FIL_D <= FIL_D1 + FIL_D2;

-- coeff(5) = coeff(27) = 32/8192 
FIL_E1 <= FIL_IN4(13) & FIL_IN4(13 downto 5);
FIL_E2 <= FIL_IN26(13) & FIL_IN26(13 downto 5);
FIL_E <= FIL_E1 + FIL_E2;

-- coeff(6) = coeff(26) = 16/8192
FIL_F1 <= FIL_IN5(13) & FIL_IN5(13 downto 6);
FIL_F2 <= FIL_IN25(13) & FIL_IN25(13 downto 6);
FIL_F <= FIL_F1 + FIL_F2;

-- coeff(7) = coeff(25) = 64/8192 
FIL_G1 <= FIL_IN6(13) & FIL_IN6(13 downto 4);
FIL_G2 <= FIL_IN24(13) & FIL_IN24(13 downto 4);
FIL_G <= FIL_G1 + FIL_G2;

-- coeff(8) = coeff(24) = 128/8192  
FIL_H1 <= FIL_IN7(13) & FIL_IN7(13 downto 3);
FIL_H2 <= FIL_IN23(13) & FIL_IN23(13 downto 3);
FIL_H <= FIL_H1 + FIL_H2;

-- coeff(9) = coeff(23) = -16/8192 
FIL_I1 <= FIL_IN8(13) & FIL_IN8(13 downto 6);
FIL_I2 <= FIL_IN22(13) & FIL_IN22(13 downto 6);
FIL_I <= FIL_I1 + FIL_I2;

-- coeff(10) = coeff(22) = -256/8192
FIL_J1 <= FIL_IN9(13) & FIL_IN9(13 downto 2);
FIL_J2 <= FIL_IN21(13) & FIL_IN21(13 downto 2);
FIL_J <= FIL_J1 + FIL_J2;

-- coeff(11) = coeff(21) = -256/8192
FIL_K1 <= FIL_IN10(13) & FIL_IN10(13 downto 2);
FIL_K2 <= FIL_IN20(13) & FIL_IN20(13 downto 2);
FIL_K <= FIL_K1 + FIL_K2;

-- coeff(12) = coeff(20) = -128/8192
FIL_L1 <= FIL_IN11(13) & FIL_IN11(13 downto 3);
FIL_L2 <= FIL_IN19(13) & FIL_IN19(13 downto 3);
FIL_L <= FIL_L1 + FIL_L2;

-- coeff(13) = coeff(19) = 256/8192 
FIL_M1 <= FIL_IN12(13) & FIL_IN12(13 downto 2);
FIL_M2 <= FIL_IN18(13) & FIL_IN18(13 downto 2);
FIL_M <= FIL_M1 + FIL_M2;

-- coeff(14) = coeff(18) = 1024/8192 
FIL_NA1 <= FIL_IN13(13) & FIL_IN13;
FIL_NA2 <= FIL_IN17(13) & FIL_IN17;
FIL_NA <= FIL_NA1 + FIL_NA2;

-- coeff(15) = coeff(17) = 2048/8192 
FIL_NB1 <= FIL_IN14(13) & FIL_IN14 & '0';
FIL_NB2 <= FIL_IN16(13) & FIL_IN16 & '0';
FIL_NB <= FIL_NB1 + FIL_NB2;


 

-- SECOND LEVEL OF ADDERS

--- FIL_A +  FIL_F	 	(16+16)
FIL_O1 <= FIL_A(8) & FIL_A;
FIL_O2 <= FIL_F(8) & FIL_F;
FIL_O <= FIL_O1 + FIL_O2;

--- FIL_B - FIL_D	 	(32-32) 
FIL_P1 <= FIL_B(9) & FIL_B;
FIL_P2 <= FIL_D(9) & FIL_D;
FIL_P <= FIL_P1 - FIL_P2;

--- FIL_C - 1/4 FIL_E	  (8-8)
FIL_Q1 <= FIL_C(7) & FIL_C;
FIL_Q2 <= FIL_E(9) & FIL_E(9 downto 2);
FIL_Q <= FIL_Q1 - FIL_Q2;

--- 1/2 FIL_G - FIL_E  		(32+32)
FIL_R1 <= FIL_G(10) & FIL_G(10 downto 1);
FIL_R2 <= FIL_E(9) & FIL_E;
FIL_R <= FIL_R1 - FIL_R2;

---  FIL_G - 1/2 FIL_L	  	(64-64)
FIL_S1 <= FIL_G(10) & FIL_G;
FIL_S2 <= FIL_L(11) & FIL_L(11 downto 1);
FIL_S <= FIL_S1 - FIL_S2;

--- FIL_H - FIL_L 		(128-128)
FIL_T1 <= FIL_H(11) & FIL_H;
FIL_T2 <= FIL_L(11) & FIL_L;
FIL_T <= FIL_T1 - FIL_T2;
		
--- FIL_I + 1/8 FIL_H	 	-(16+16)
FIL_U1 <= FIL_I(8) & FIL_I;
FIL_U2 <= FIL_H(11) & FIL_H(11 downto 3);
FIL_U <= FIL_U1 + FIL_U2;
		
--- 1/16 FIL_K + 1/16 FIL_J	  	(16+16)
FIL_V1 <= FIL_K(12) & FIL_K(12 downto 4);
FIL_V2 <= FIL_J(12) & FIL_J(12 downto 4);
FIL_V <= FIL_V1 + FIL_V2;
		
--- 1/2 FIL_M - 1/2 FIL_K			(128-128)
FIL_W1 <= FIL_M(12) & FIL_M(12 downto 1);
FIL_W2 <= FIL_K(12) & FIL_K(12 downto 1);
FIL_W <= FIL_W1 - FIL_W2;
	
--- FIL_K + FIL_J		-(256+256)
FIL_X1 <= FIL_K(12) & FIL_K;
FIL_X2 <= FIL_J(12) & FIL_J;
FIL_X <= FIL_X1 + FIL_X2;

--- FIL_M + 1/4 FIL_NA			(256+256)
FIL_XB1 <= FIL_M(12) & FIL_M;
FIL_XB2 <= FIL_NA(14) & FIL_NA(14 downto 2);
FIL_XB <= FIL_XB1 + FIL_XB2;

--- 1/8 FIL_IN15 + FIL_NA (256+1024)
FIL_XD1(11 downto 0) <= FIL_IN15(13 downto 2);
FIL_XD1(15 downto 12) <= (others => FIL_IN15(13));
FIL_XD2 <= FIL_NA(14) & FIL_NA;
FIL_XD <= FIL_XD1 + FIL_XD2;

--- 1/16 FIL_NA + 1/32 FIL_NB 	-(64+64)
FIL_XE1 <= FIL_NA(14) & FIL_NA(14 downto 4);
FIL_XE2 <= FIL_NB(15) & FIL_NB(15 downto 5);
FIL_XE <= FIL_XE1 + FIL_XE2;

--- FIL_IN15 + FIL_NB  		(2048+2048)
FIL_XG1 <= FIL_IN15(13) & FIL_IN15(13) & FIL_IN15 & '0';
FIL_XG2 <= FIL_NB(15) & FIL_NB;
FIL_XG <= FIL_XG1 + FIL_XG2;

		
-- THIRD LEVEL OF ADDERS  
RECLOCK_001: process(CLK)
begin   
	if rising_edge(CLK) then
		FIL_IN15_D <= FIL_IN15(13) & FIL_IN15(13) & FIL_IN15(13 downto 5);
		FIL_O_D <= FIL_O;
		FIL_P_D <= FIL_P;
		FIL_Q_D <= FIL_Q;
		FIL_R_D <= FIL_R;
		FIL_S_D <= FIL_S;
		FIL_T_D <= FIL_T;
		FIL_U_D <= FIL_U;
		FIL_V_D <= FIL_V;
		FIL_W_D <= FIL_W;
		FIL_X_D <= FIL_X;
		FIL_XA_D <= FIL_XA;
		FIL_XB_D <= FIL_XB;
		FIL_XC_D <= FIL_XC;
		FIL_XD_D <= FIL_XD;
		FIL_XE_D <= FIL_XE;
		FIL_XG_D <= FIL_XG;
	end if;
end process;

--- FIL_P_D + FIL_R_D  (32+32)
FIL_Y1 <= FIL_P_D(10) & FIL_P_D;
FIL_Y2 <= FIL_R_D(10) & FIL_R_D;
FIL_Y <= FIL_Y1 + FIL_Y2;

--- FIL_O_D + FIL_U_D	(16-16)
FIL_Z1 <= FIL_O_D(9) & FIL_O_D;
FIL_Z2 <= FIL_U_D(9) & FIL_U_D;
FIL_Z <= FIL_Z1 - FIL_Z2;

--- FIL_T_D + FIL_W_D	 (128+128)
FIL_AA1 <= FIL_T_D(12) & FIL_T_D;
FIL_AA2 <= FIL_W_D(12) & FIL_W_D;
FIL_AA <= FIL_AA1 + FIL_AA2;

--- FIL_S_D + FIL_XE_D  (64-64)
FIL_BB1 <= FIL_S_D(11) & FIL_S_D;
FIL_BB2 <= FIL_XE_D(11) & FIL_XE_D;
FIL_BB <= FIL_BB1 - FIL_BB2;

--- FIL_V_D - FIL_IN15_D (16-32)
FIL_CC1 <= FIL_V_D(9) & FIL_V_D(9) & FIL_V_D;
FIL_CC2 <= FIL_IN15_D(10) & FIL_IN15_D;
FIL_CC <= FIL_CC1 - FIL_CC2;

--- FIL_XB_D - FIL_X_D (256-256)
FIL_DDA1 <= FIL_XB_D(13) & FIL_XB_D;
FIL_DDA2 <= FIL_X_D(13) & FIL_X_D;
FIL_DDA <= FIL_DDA1 - FIL_DDA2;

--- FIL_XG_D + FIL_XD_D (2048+1024)
FIL_DDC1 <= FIL_XG_D(16) & FIL_XG_D;
FIL_DDC2 <= FIL_XD_D(15) & FIL_XD_D(15) & FIL_XD_D;
FIL_DDC <= FIL_DDC1 + FIL_DDC2;
		

-- FOURTH LEVEL OF ADDERS
--- FIL_Y + FIL_CC	 (32+32)
FIL_EE1 <= FIL_Y(11) & FIL_Y;
FIL_EE2 <= FIL_CC(11) & FIL_CC;
FIL_EE <= FIL_EE1 + FIL_EE2;

--- FIL_Z + FIL_Q_D(16+8)
FIL_FF1 <= FIL_Z(10) & FIL_Z;
FIL_FF2(8 downto 0) <= FIL_Q_D;
FIL_FF2(11 downto 9) <= (others => FIL_Q_D(8));
FIL_FF <= FIL_FF1 + FIL_FF2;

--- FIL_CC + FIL_X_D (64+64)
--FIL_GG1 <=  FIL_CC(12) & FIL_CC;
--FIL_GG2 <= FIL_X_D(11) & FIL_X_D(11) & FIL_X_D;
--FIL_GG <= FIL_GG1 + FIL_GG2;

--- FIL_AA + FIL_BB (128+64)
FIL_GGA1 <=  FIL_AA(13) & FIL_AA;
FIL_GGA2 <= FIL_BB(12) & FIL_BB(12) & FIL_BB;
FIL_GGA <= FIL_GGA1 + FIL_GGA2;
		
--- FIL_DDC + FIL_DDA (2048+256)
FIL_GGB1 <=  FIL_DDC(17) & FIL_DDC;
FIL_GGB2(14 downto 0) <= FIL_DDA;
FIL_GGB2(18 downto 15) <= (others => FIL_DDA(14));
FIL_GGB <= FIL_GGB1 + FIL_GGB2;


-- FIFTH LEVEL OF ADDERS  
RECLOCK_002: process(CLK)
begin   
	if rising_edge(CLK) then
		FIL_EE_D <= FIL_EE;
		FIL_FF_D <= FIL_FF;
		FIL_GGA_D <= FIL_GGA;
		FIL_GGB_D <= FIL_GGB;
	end if;
end process;


-- FIL_FF_D + FIL_EE_D	  (16+32)
FIL_HH1 <= FIL_FF_D(11) & FIL_FF_D(11) & FIL_FF_D;
FIL_HH2 <= FIL_EE_D(12) & FIL_EE_D;
FIL_HH <= FIL_HH1 + FIL_HH2;

-- FIL_GGA_D + FIL_GGB_D	  (2048+128)
FIL_HHA1(14 downto 0) <= FIL_GGA_D;
FIL_HHA1(19 downto 15) <= (others => FIL_GGA_D(14));
FIL_HHA2 <= FIL_GGB_D(18) & FIL_GGB_D;
FIL_HHA <= FIL_HHA1 + FIL_HHA2;


-- SIXTH LEVEL OF ADDERS  
RECLOCK_003: process(CLK)
begin   
	if rising_edge(CLK) then
		FIL_HHA_D <= FIL_HHA;
		FIL_HH_D <= FIL_HH;
	end if;
end process;

-- FIL_HHA + FIL_HH (2048+32)
FIL_II1 <= FIL_HHA_D(19) & FIL_HHA_D;
FIL_II3(13 downto 0) <= FIL_HH_D;
FIL_II3(20 downto 14) <= (others => FIL_HH_D(13));
FIL_II <= FIL_II1 + FIL_II3;


-- clip output to 13 bits (same number of bits as input)  
-- Should be OK since the filter has a maximum gain of 1.
CLIP001: process(CLK)
begin                         
	if rising_edge(CLK) then
		if(FIL_II(20) = '1') and (FIL_II(19 downto 16) /= "1111") then	-- overflow negative
			FIL_LL <= "10000000000001";	-- most negative
		elsif(FIL_II(20) = '0') and (FIL_II(19 downto 16) /= "0000") then	-- overflow positive
			FIL_LL <= "01111111111111";	-- most positive
		else	-- within range
			FIL_LL <= FIL_II(16 downto 3);
		end if;		
	end if;
end process;
		
DATA_OUT <= FIL_LL;

RECLOCK_004: process(CLK)
begin
	-- Generate the output sample clock
	if rising_edge(CLK) then
		SAMPLE_CLK_IN_D <= SAMPLE_CLK_IN;
		SAMPLE_CLK_IN_D2 <= SAMPLE_CLK_IN_D;
		SAMPLE_CLK_IN_D3 <= SAMPLE_CLK_IN_D2;
		SAMPLE_CLK_IN_D4 <= SAMPLE_CLK_IN_D3;
		SAMPLE_CLK_OUT <= SAMPLE_CLK_IN_D4;
	end if;
end process;

end behavior;					