----------------------------------------------
-- MSS copyright 1999-2001
-- Filename: ROM64X8.VHD
-- Author: Alain Zarembowitch / MSS
-- Inheritance: new
-- Edit date: 1-29-01
-- Revision: 0.002
--  Description:
--  Sinewave table, 90 deg
--  Latency is 2 CLK
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--  
--
entity ROM64x8 IS  
  port( A: in std_logic_vector(5 downto 0);
		CLK: in std_logic;
		ASYNC_RESET: in std_logic;
 		Q: out std_logic_vector(7 downto 0)
  );
end ROM64x8;
--
--  behavior describing a parameterized ROM
architecture BEHAVIOR of ROM64x8 is

signal Q0: std_logic_vector(7 downto 0) := (others => '0');
signal Q1: std_logic_vector(7 downto 0) := (others => '0');
signal Q2: std_logic_vector(7 downto 0) := (others => '0');
signal Q3: std_logic_vector(7 downto 0) := (others => '0');
signal Q4: std_logic_vector(7 downto 0) := (others => '0');
signal Q5: std_logic_vector(7 downto 0) := (others => '0');
signal Q6: std_logic_vector(7 downto 0) := (others => '0');
signal Q7: std_logic_vector(7 downto 0) := (others => '0');
signal A_D: std_logic_vector(2 downto 0) := (others => '0');

begin

-- delay 3 MSB of A so as to be synchronous with the Q0-Q7
process (CLK, ASYNC_RESET, A)
begin
	if(ASYNC_RESET = '1') then
		A_D <= "000";
	elsif rising_edge(CLK) then
		A_D <= A(5 downto 3);
	end if;
end process;

process (CLK, ASYNC_RESET, A)
begin
	if(ASYNC_RESET = '1') then
		Q0 <= "00000000";
	elsif rising_edge(CLK) then
		case A(2 downto 0) is
		  when "000"=>
		  	Q0 <= "00000011";
		  when "001"=>
		  	Q0 <= "00001001";
		  when "010"=>
		  	Q0 <= "00001111";
		  when "011"=>
		  	Q0 <= "00010101";
		  when "100"=>
		  	Q0 <= "00011100";
		  when "101"=>
		  	Q0 <= "00100010";
		  when "110"=>
		  	Q0 <= "00101000";
		  when others=>
		  	Q0 <= "00101110";
		end case;
	end if;
end process;

process (CLK, ASYNC_RESET, A)
begin
	if(ASYNC_RESET = '1') then
		Q1 <= "00000000";
	elsif rising_edge(CLK) then
		case A(2 downto 0) is
 		  when "000"=>
		  	Q1 <= "00110101";
		  when "001"=>
		  	Q1 <= "00111011";
		  when "010"=>
		  	Q1 <= "01000001";
		  when "011"=>
		  	Q1 <= "01000111";
		  when "100"=>
		  	Q1 <= "01001101";
		  when "101"=>
		  	Q1 <= "01010011";
		  when "110"=>
		  	Q1 <= "01011001";
		  when others=>
		  	Q1 <= "01011111";
		end case;
	end if;
end process;


process (CLK, ASYNC_RESET, A)
begin
	if(ASYNC_RESET = '1') then
		Q2 <= "00000000";
	elsif rising_edge(CLK) then
		case A(2 downto 0) is
 		  when "000"=>
		  	Q2 <= "01100100";
 		  when "001"=>
		  	Q2 <= "01101010";
		  when "010"=>
		  	Q2 <= "01110000";
		  when "011"=>
		  	Q2 <= "01110101";
		  when "100"=>
		  	Q2 <= "01111011";
		  when "101"=>
		  	Q2 <= "10000000";
		  when "110"=>
		  	Q2 <= "10000110";
		  when others=>
		  	Q2 <= "10001011";
		end case;
	end if;
end process;



process (CLK, ASYNC_RESET, A)
begin
	if(ASYNC_RESET = '1') then
		Q3 <= "00000000";
	elsif rising_edge(CLK) then
		case A(2 downto 0) is
 		  when "000"=>
		  	Q3 <= "10010000";
		  when "001"=>
		  	Q3 <= "10010101";
		  when "010"=>
		  	Q3 <= "10011011";
		  when "011"=>
		  	Q3 <= "10011111";
		  when "100"=>
		  	Q3 <= "10100100";
		  when "101"=>
		  	Q3 <= "10101001";
		  when "110"=>
		  	Q3 <= "10101110";
		  when others=>
		  	Q3 <= "10110010";
		end case;
	end if;
end process;


process (CLK, ASYNC_RESET, A)
begin
	if(ASYNC_RESET = '1') then
		Q4 <= "00000000";
	elsif rising_edge(CLK) then
		case A(2 downto 0) is
		  when "000"=>
		  	Q4 <= "10110111";
		  when "001"=>
		  	Q4 <= "10111011";
		  when "010"=>
		  	Q4 <= "10111111";
		  when "011"=>
		  	Q4 <= "11000011";
		  when "100"=>
		  	Q4 <= "11000111";
		  when "101"=>
		  	Q4 <= "11001011";
		  when "110"=>
		  	Q4 <= "11001111";
		  when others=>
		  	Q4 <= "11010011";
		end case;
	end if;
end process;

process (CLK, ASYNC_RESET, A)
begin
	if(ASYNC_RESET = '1') then
		Q5 <= "00000000";
	elsif rising_edge(CLK) then
		case A(2 downto 0) is
		  when "000"=>
		  	Q5 <= "11010110";
		  when "001"=>
		  	Q5 <= "11011001";
		  when "010"=>
		  	Q5 <= "11011101";
		  when "011"=>
		  	Q5 <= "11100000";
		  when "100"=>
		  	Q5 <= "11100011";
		  when "101"=>
		  	Q5 <= "11100110";
		  when "110"=>
		  	Q5 <= "11101000";
		  when others=>
		  	Q5 <= "11101011";
		end case;
	end if;
end process;

process (CLK, ASYNC_RESET, A)
begin
	if(ASYNC_RESET = '1') then
		Q6 <= "00000000";
	elsif rising_edge(CLK) then
		case A(2 downto 0) is
		  when "000"=>
		  	Q6 <= "11101101";
		  when "001"=>
		  	Q6 <= "11101111";
		  when "010"=>
		  	Q6 <= "11110010";
		  when "011"=>
		  	Q6 <= "11110100";
		  when "100"=>
		  	Q6 <= "11110101";
		  when "101"=>
		  	Q6 <= "11110111";
		  when "110"=>
		  	Q6 <= "11111001";
		  when others=>
		  	Q6 <= "11111010";
		end case;
	end if;
end process;

process (CLK, ASYNC_RESET, A)
begin
	if(ASYNC_RESET = '1') then
		Q7 <= "00000000";
	elsif rising_edge(CLK) then
		case A(2 downto 0) is
		  when "000"=>
		  	Q7 <= "11111011";
		  when "001"=>
		  	Q7 <= "11111100";
		  when "010"=>
		  	Q7 <= "11111101";
		  when "011"=>
		  	Q7 <= "11111110";
		  when others=>
 		  	Q7 <= "11111111";
		end case;
  	end if;
end process;

process (CLK, ASYNC_RESET, A_D, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7)
begin
	if(ASYNC_RESET = '1') then
		Q <= "00000000";
	elsif rising_edge(CLK) then
		case A_D is
			when "000"=>
				Q <= Q0;
			when "001"=>
				Q <= Q1;
			when "010"=>
				Q <= Q2;
			when "011"=>
				Q <= Q3;
			when "100"=>
				Q <= Q4;
			when "101"=>
				Q <= Q5;
			when "110"=>
				Q <= Q6;
		  when others=>
				Q <= Q7;
		end case;
  	end if;
end process;

end BEHAVIOR;
