-- Rev 8 8-10-02 AZ
-- Displays rev number
-- Add DAC clock for connection to COM-2001
-- 
-- Rev 9 8-20-02 AZ
-- corrected BER monitoring registers assignment.
--
-- Rev 10 11-11-02 AZ
-- Improved the spectral density flatness.
-- Changed uc interface to remove potential conflict between FPGA and flash memory(for next rev)
--
-- Rev 11 12-15-02 AZ
-- removed conflict on J2(13), SAMPLE_CLK_IN_REQ
-- Added power measurement on signal and noise prior to scaling
-- Added overflow detection feature.
-- Added clamping when overflow occurs
--
-- Rev 12 10-21-03 AZ
-- Added ability to control noise bandwidth. REG6/7/8
-- Inverted output clock CLK_OUT for better timing

Rev 13 7/7/06 AZ
Converted project to ISE 7.1

