--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:07:05 07/18/2012
-- Design Name:   
-- Module Name:   C:/Users/AK/Documents/source_VHDL/com-1509 Viterbi decoder/sim/tb_va.vhd
-- Project Name:  com1509
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Viterbi_decoder
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.com1509pkg.all;	-- defines global types, key configuration parameters to be defined at synthesis time.

ENTITY tb_va IS
END tb_va;
 
ARCHITECTURE behavior OF tb_va IS 
 
--------------------------------------------------------
--      COMPONENTS
----------------------------------------------------------
	COMPONENT VA
	GENERIC(
		BER_MEASUREMENT_EN: std_logic
			-- enable optional BER measurement
	);
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATAIN: in slv4xN_PARITY_BITS_MAX;	
		ERASURES: in std_logic_vector((N_PARITY_BITS_MAX - 1) downto 0);	
		INPUT_VALID : IN std_logic;     
		G: in slvGENPOLYxN_PARITY_BITS_MAX;
		N_PARITY_BITS: in integer range 2 to 7;
		K: in integer range 3 to 9;
		DECODED_BITS: out std_logic_vector(TB_DEPTH-1 downto 0);
		DECODED_BITS_VALID: out std_logic;
		DECODED_BIT: out std_logic;
		DECODED_BIT_VALID: out std_logic;
		BER: out std_logic_vector(31 downto 0) := (others => '0');
		BER_VALID: out std_logic
		);
	END COMPONENT;

	COMPONENT INFILE2SIM
	 GENERIC (
		N_COLS: integer;	
		FILENAME: string
	 );
	PORT(
		CLK : IN std_logic;
		SAMPLE_CLK_IN : IN std_logic;          
		DATA1 : OUT std_logic_vector(11 downto 0);
		DATA2 : OUT std_logic_vector(11 downto 0);
		DATA3 : OUT std_logic_vector(11 downto 0)
		);
	END COMPONENT;

--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
   signal CLK : std_logic := '0';
   signal SYNC_RESET : std_logic := '0';
   signal SAMPLE_CLK_IN : std_logic := '0';
	signal STIMULUS: std_logic_vector(11 downto 0):= (others => '0');
	signal BIT_CNTR: std_logic_vector(2 downto 0) := "111";
	signal INPUT_VALID: std_logic := '0';
   signal DATAIN : slv4xN_PARITY_BITS_MAX := (others => (others => '0'));
   signal ERASURES : std_logic_vector((N_PARITY_BITS_MAX-1) downto 0):= (others => '0');
	signal READ_CNTR: std_logic_vector(1 downto 0) := (others => '0');
	signal G: slvGENPOLYxN_PARITY_BITS_MAX := (others => (others => '0')); 
	signal N_PARITY_BITS: integer range 2 to 7 := 2;
	signal K: integer range 3 to 9 := 7;


   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
BEGIN
   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin		
		SYNC_RESET <= '1';
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		SYNC_RESET <= '0';

      wait for CLK_period*10;
      wait;
   end process;

	-- read stimulus file as fast as possible
	SAMPLE_CLK_IN <= not SYNC_RESET;
--	-- read at slower pace
--	READ_SLOW: process(CLK)
--	begin
--		if rising_edge(CLK) then
--			READ_CNTR <= READ_CNTR + 1;
--			if(READ_CNTR = 0) then
--				SAMPLE_CLK_IN <= '1';
--			else
--				SAMPLE_CLK_IN <= '0';
--			end if;
--		end if;
--	end process;

	-- read stimulus file 
 	-- Baseband input stream 4-bit soft quantized samples. Range 0 - 15
	Inst_INFILE2SIM: INFILE2SIM 
	generic map(
		N_COLS => 1,
		FILENAME => ".\sim\fecdataout.txt"	
	)
	PORT MAP(
		CLK => CLK,
		SAMPLE_CLK_IN => SAMPLE_CLK_IN,
		DATA1 => STIMULUS,
		DATA2 => open,
		DATA3 => open
	);

	-- collect N_PARITY_BITS before sending the encoded group to the Viterbi algorithm for decoding
	BIT_CNTR_GEN: process(CLK)
	begin
		if rising_edge(CLK) then
			if(SAMPLE_CLK_IN = '1') then
				if(BIT_CNTR = N_PARITY_BITS - 1) then
					BIT_CNTR <= (others => '0');	-- modulo N_PARITY_BITS counter
					INPUT_VALID <= '1';
				else
					BIT_CNTR <= BIT_CNTR + 1;
					INPUT_VALID <= '0';
				end if;
			else
				INPUT_VALID <= '0';
			end if;
		end if;
	end process;

	-- 4-bit soft-quantized
	DATAIN_GEN: for I in 0 to N_PARITY_BITS_MAX -1 generate
		DATAIN_GEN: process(CLK)
		begin
			if rising_edge(CLK) then
				if(SAMPLE_CLK_IN = '1') then
					if(BIT_CNTR = I) then
						DATAIN(I) <= STIMULUS(3 downto 0);	
					end if;
				end if;
			end if;
		end process;
	end generate;
 
	-- Instantiate the Unit Under Test (UUT)
	-- generator polynomials
	G(0) <= O"171";
	G(1) <= O"133";
	N_PARITY_BITS <= 2;
	
	uut: VA 
	generic map(
		BER_MEASUREMENT_EN => '1'
	)
	PORT MAP(
		CLK => CLK,
		SYNC_RESET => SYNC_RESET,
		DATAIN => DATAIN,
		ERASURES => ERASURES,
		INPUT_VALID => INPUT_VALID,
		G => G,
		N_PARITY_BITS => N_PARITY_BITS,
		K => K,
		DECODED_BITS => open,
		DECODED_BITS_VALID => open,
		DECODED_BIT => open,
		DECODED_BIT_VALID => open,
		BER => open,
		BER_VALID => open
	);

END;
