library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_BER_GEN is end test_BER_GEN;

architecture testbench of test_BER_GEN is

-- Declaration of the component under test
component BER_GEN
  port (
     TP : out std_logic_vector(9 downto 0);
     TX_R : out std_logic;
     TX_B : out std_logic;
     TX_L : out std_logic;
     RX_R : in std_logic;
     RX_B : in std_logic;
     RX_L : in std_logic;
     UC_FLASH_CSN : in std_logic;
     UC_ALE_IN : in std_logic;
     UC_RDN : in std_logic;
     UC_WRN_IN : in std_logic;
     UC_AD : inout std_logic_vector(7 downto 0);
     CONTROL : in std_logic_vector(7 downto 0);
     J4 : inout std_logic_vector(29 downto 1);
     J3 : inout std_logic_vector(29 downto 1);
     J2 : inout std_logic_vector(29 downto 2);
     CLK_IN2 : in std_logic;
     CLK_IN1 : in std_logic
      );
end component;

signal   TP : std_logic_vector(9 downto 0);
signal   TX_R : std_logic;
signal   TX_B : std_logic;
signal   TX_L : std_logic;
signal   RX_R : std_logic;
signal   RX_B : std_logic;
signal   RX_L : std_logic;
signal   UC_FLASH_CSN : std_logic;
signal   UC_ALE_IN : std_logic;
signal   UC_RDN : std_logic;
signal   UC_WRN_IN : std_logic;
signal   UC_AD : std_logic_vector(7 downto 0);
signal   CONTROL : std_logic_vector(7 downto 0);
signal   J4 : std_logic_vector(29 downto 1);
signal   J3 : std_logic_vector(29 downto 1);
signal   J2 : std_logic_vector(29 downto 2);
signal   CLK_IN2 : std_logic;
signal   CLK_IN1 : std_logic;

begin

-- Place stimulus and analysis statements here      
process
begin
	CLK_IN2 <= '0';
	wait for 5 ns;
	CLK_IN2 <= '1';
	wait for 5 ns;
end process;

RX_R <= '0';
RX_L <= '0';
RX_B <= '0';
UC_ALE_IN <= '0';
UC_WRN_IN <= '1';
UC_FLASH_CSN <= '1';
UC_RDN <= '1';     

J2(2) <= J2(13);	-- loopback clock requests
J2(3) <= '0';



dut :  BER_GEN  port map (
     TP => TP,
     TX_R => TX_R,
     TX_B => TX_B,
     TX_L => TX_L,
     RX_R => RX_R,
     RX_B => RX_B,
     RX_L => RX_L,
     UC_FLASH_CSN => UC_FLASH_CSN,
     UC_ALE_IN => UC_ALE_IN,
     UC_RDN => UC_RDN,
     UC_WRN_IN => UC_WRN_IN,
     UC_AD => UC_AD,
     CONTROL => CONTROL,
     J4 => J4,
     J3 => J3,
     J2 => J2,
     CLK_IN2 => CLK_IN2,
     CLK_IN1 => CLK_IN1
      );

end testbench;
