--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:05:15 04/09/2013
-- Design Name:   
-- Module Name:   C:/Users/AK/Documents/source_VHDL/com-0005 BMS DSSSdemod 007/src/divider/tbdivider.vhd
-- Project Name:  divider
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DIVIDER
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tbdivider IS
END tbdivider;
 
ARCHITECTURE behavior OF tbdivider IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DIVIDER
	 Generic(
		NBITS: integer
	 );
    PORT(
         CLK : IN  std_logic;
         NUM : IN  std_logic_vector((NBITS-1) downto 0);
         DENOM : IN  std_logic_vector((NBITS-1) downto 0);
         SAMPLE_CLK_IN : IN  std_logic;
         QUOTIENT : OUT  std_logic_vector((NBITS-1) downto 0);
         REMAINDER : OUT  std_logic_vector((NBITS-1) downto 0);
         SAMPLE_CLK_OUT : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
	constant NBITS: integer := 4;
   signal CLK : std_logic := '0';
   signal NUM : std_logic_vector((NBITS-1) downto 0) := "1110";
   signal DENOM : std_logic_vector((NBITS-1) downto 0) := "0011";
   signal SAMPLE_CLK_IN : std_logic := '0';

 	--Outputs
   signal QUOTIENT : std_logic_vector((NBITS-1) downto 0);
   signal REMAINDER : std_logic_vector((NBITS-1) downto 0);
   signal SAMPLE_CLK_OUT : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DIVIDER 
	GENERIC MAP(
		NBITS => NBITS
	)
	PORT MAP (
          CLK => CLK,
          NUM => NUM,
          DENOM => DENOM,
          SAMPLE_CLK_IN => SAMPLE_CLK_IN,
          QUOTIENT => QUOTIENT,
          REMAINDER => REMAINDER,
          SAMPLE_CLK_OUT => SAMPLE_CLK_OUT
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
		SAMPLE_CLK_IN <= '0';
      wait for 100 ns;	
		SAMPLE_CLK_IN <= '1';
      wait for CLK_period;
		SAMPLE_CLK_IN <= '0';
      wait;
   end process;

END;
