testing the 4004 interface on the left side of COM-1800
The firmware is COM-1827 CPM modem, but the principle is the same for the com-1831
Due to time limitation, the output timing may not be fully optimum (still a few minor glitches on the 70 MHz output spectrum)
The timing is adjusted in this line:     CLKOUT0_PHASE        => 270.000,	-- ADJUST TIMING HERE
A picture in this folder illustrates the assembly: both COM-4004 and COM-18XX are facing up, COM-4004 on the left side of COM-1800.

IMPORTANT: In order to avoid resampling on the tx path (which would be bad for spectrum sidelobes level),
it is important to use the fixed-frequency 50 MHz CLK_TXg as a reference to the digital modulator.
This means that the only possible chip rates are 25 Mchips/s, 12.5 Mchips/s, 6.125 Mchips/s, etc
or more generally 50 MHz / 2^n, where n is an integer greater or equal to 1.
The division factor is usually called SYMBOL_RATE_NDIV in the VHDL code.

