-------------------------------------------------------------
-- MSS copyright 2015
-- Filename:  BM_PARTIAL_GEN.VHD
-- Authors: 
--		Alain Zarembowitch / MSS
-- Version: Rev 0
-- Last modified: 11/9/15

-- Inheritance: 	N/A
--
-- description:  Generate the 4 partial branch metrics value, based on the received parity bits YW and the
-- associated erasure information (when puncturing is enabled). Latency: 1 CLK
-------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity BM_PARTIAL_GEN is
	generic (
		NQBITS: integer range 3 to 8 := 4
			-- number of soft-quantized bits at the decoder input
	);
    Port ( 
		--GLOBAL CLOCKS
		CLK: std_logic;
		
		-- Inputs
		-- received samples YW at time k
		Y : IN std_logic_vector((NQBITS-1) downto 0);          
		W : IN std_logic_vector((NQBITS-1) downto 0);   
			-- signed format
		ERASURE_Y: in std_logic;
		ERASURE_W: in std_logic;
		IN_VALID: in std_logic;
			-- '1' when the above inputs are valid

		-- branch metrics at time k
		BM0 : out std_logic_vector((NQBITS+1) downto 0);          
		BM1 : out std_logic_vector((NQBITS+1) downto 0);          
		BM2 : out std_logic_vector((NQBITS+1) downto 0);          
		BM3 : out std_logic_vector((NQBITS+1) downto 0);          
		OUT_VALID: out std_logic
  );
end entity;

architecture Behavioral of BM_PARTIAL_GEN is
--------------------------------------------------------
--      COMPONENTS
--------------------------------------------------------
--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
-- Suffix _D indicates a one CLK delayed version of the net with the same name
-- Suffix _X indicates an extended precision version of the net with the same name
-- Suffix _N indicates an inverted version of the net with the same name

signal YE: signed((NQBITS+1) downto 0) := (others => '0');  
signal WE: signed((NQBITS+1) downto 0) := (others => '0');  

--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
begin

YE <= resize(signed(Y),NQBITS+2) when (ERASURE_Y = '0') else (others => '0');
WE <= resize(signed(W),NQBITS+2) when (ERASURE_W = '0') else (others => '0');

BM_GEN_001: process(CLK)
begin
	if rising_edge(CLK) then
		OUT_VALID <= IN_VALID;
		
		if(IN_VALID = '1') then
			BM0 <= std_logic_vector(- YE - WE) ;
			BM1 <= std_logic_vector(- YE + WE) ;
			BM2 <= std_logic_vector(YE - WE) ;
			BM3 <= std_logic_vector(YE + WE) ;
		end if;
	end if;
end process;
	

end Behavioral;

