Release 8.2i par I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

HP5::  Wed Sep 02 14:52:47 2009

par -w -intstyle ise -ol med -t 1 BER_GEN_map.ncd BER_GEN.ncd BER_GEN.pcf 


Constraints file: BER_GEN.pcf.
Loading device for application Rf_Device from file 'v200.nph' in environment C:\Xilinx.
   "BER_GEN" is an NCD, version 3.1, device xc2s200, package pq208, speed -6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)


Device speed data version:  "PRODUCTION 1.27 2006-05-03".


Device Utilization Summary:

   Number of BLOCKRAMs                 5 out of 14     35%
   Number of GCLKs                     3 out of 4      75%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         1 out of 1     100%

   Number of External IOBs            98 out of 140    70%
      Number of LOCed IOBs            97 out of 98     98%

   Number of SLICEs                 1694 out of 2352   72%


Overall effort level (-ol):   Medium
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Medium

Starting initial Timing Analysis.  REAL time: 3 secs 
Finished initial Timing Analysis.  REAL time: 3 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:990643) REAL time: 4 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 4 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
..................................................
........................................
..................................................
............................................................
...................................
..............
Phase 6.8 (Checksum:df25c7) REAL time: 25 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 25 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 34 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 34 secs 

Writing design to file BER_GEN.ncd


Total REAL time to Placer completion: 36 secs 
Total CPU time to Placer completion: 36 secs 

Starting Router

Phase 1: 10787 unrouted;       REAL time: 36 secs 

Phase 2: 9719 unrouted;       REAL time: 40 secs 

Phase 3: 2230 unrouted;       REAL time: 42 secs 

Phase 4: 2230 unrouted; (0)      REAL time: 43 secs 

Phase 5: 2230 unrouted; (0)      REAL time: 43 secs 

Phase 6: 2230 unrouted; (0)      REAL time: 43 secs 

Phase 7: 0 unrouted; (0)      REAL time: 45 secs 

Phase 8: 0 unrouted; (0)      REAL time: 46 secs 

Total REAL time to Router completion: 47 secs 
Total CPU time to Router completion: 47 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 CLK |      GCLKBUF1| No   |  905 |  0.366     |  0.560      |
+---------------------+--------------+------+------+------------+-------------+
|              UC_WRN |      GCLKBUF0| No   |   43 |  0.089     |  0.544      |
+---------------------+--------------+------+------+------------+-------------+
|              UC_ALE |      GCLKBUF3| No   |    4 |  0.000     |  0.559      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.564
   The MAXIMUM PIN DELAY IS:                               7.173
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   6.067

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
        4165        3579        1586         850         487           0

Timing Score: 0

Number of Timing Constraints that were not applied: 2

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------
  TS_CLK_IN2 = PERIOD TIMEGRP "CLK_IN2" 20  | 20.000ns   | 18.157ns   | 9      | 1.843ns    | 0       
  ns HIGH 50%                               |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  TS_UC_ALE_IN = PERIOD TIMEGRP "UC_ALE_IN" | N/A        | N/A        | N/A    | N/A        | N/A     
   20 ns HIGH 50%                           |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  TS_UC_WRN_IN = PERIOD TIMEGRP "UC_WRN_IN" | N/A        | N/A        | N/A    | N/A        | N/A     
   20 ns HIGH 50%                           |            |            |        |            |         
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 54 secs 
Total CPU time to PAR completion: 52 secs 

Peak Memory Usage:  173 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file BER_GEN.ncd



PAR done!
