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-- Company: 
-- Engineer:
--
-- Create Date:   11:07:35 06/22/2012
-- Design Name:   
-- Module Name:   C:/Users/Alain/Documents/source_VHDL/AWGN/sim/tbAGWN.vhd
-- Project Name:  AWGN
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: AWGN
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tbAGWN IS
END tbAGWN;
 
ARCHITECTURE behavior OF tbAGWN IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT AWGN
    PORT(
         ASYNC_RESET : IN  std_logic;
         CLK : IN  std_logic;
         SAMPLE_CLK_REQ : IN  std_logic;
         SYNC_RESET : IN  std_logic;
         SAMPLE_CLK_OUT : OUT  std_logic;
         NOISE_SAMPLE1_OUT : OUT  std_logic_vector(15 downto 0);
         NOISE_SAMPLE2_OUT : OUT  std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal ASYNC_RESET : std_logic := '0';
   signal CLK : std_logic := '0';
   signal SAMPLE_CLK_REQ : std_logic := '0';
   signal SYNC_RESET : std_logic := '0';

 	--Outputs
   signal SAMPLE_CLK_OUT : std_logic;
   signal NOISE_SAMPLE1_OUT : std_logic_vector(15 downto 0);
   signal NOISE_SAMPLE2_OUT : std_logic_vector(15 downto 0);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: AWGN PORT MAP (
          ASYNC_RESET => ASYNC_RESET,
          CLK => CLK,
          SAMPLE_CLK_REQ => SAMPLE_CLK_REQ,
          SYNC_RESET => SYNC_RESET,
          SAMPLE_CLK_OUT => SAMPLE_CLK_OUT,
          NOISE_SAMPLE1_OUT => NOISE_SAMPLE1_OUT,
          NOISE_SAMPLE2_OUT => NOISE_SAMPLE2_OUT
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
	SAMPLE_CLK_REQ <= '1';	-- maximum throughput
	

END;
