-------------------------------------------------------------
-- MSS copyright 2016-2017
-- Filename:  COM1827_RX.VHD
-- Authors: 
--		Alain Zarembowitch / MSS
-- Version: 0
-- Last modified: 8/24/17

-- Inheritance: 	COM1826 4/12/15, COM1518 6/27/14
--
-- description:  CPM receiver 
---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity COM1827_RX is
	generic (
		BER_EN: std_logic := '0';
			-- instantiate BER2 measurement (1) or not (0)
			-- Note: for most applications, this BERT is disabled, as another BERT is embodied at higher level,
			--  after the FEC decoder.
		SIMULATION: std_logic := '0'
			-- 1 during simulation, 0 for release	
	);
    Port ( 
		--GLOBAL CLOCKS
		CLK: in std_logic;
			-- A/D converter clock. Global (no BUFG used within)
		SYNC_RESET: in std_logic;
			-- Component MUST be reset upon configuration or configuration change
		
		--// ADC interface
		ADC_DATA_I_IN: in std_logic_vector(15 downto 0);	-- ADC data, use MSbs, 2's complement
		ADC_DATA_Q_IN: in std_logic_vector(15 downto 0);	-- ADC data, use MSbs, 2's complement
		ADC_SAMPLE_CLK_IN: in std_logic;
			-- ADC samples, in-phase(I) and quadrature (Q)
			-- Use both I and Q in the case of near-zero center frequency input signal
			-- Use I only (force Q to zero) in the case of IF input signal, IF undesampling for example.
			-- Samples are read at the rising edge of the ADC sampling clock CLK
			-- In the case of lower precision ADCs, align the samples to the left (MSb) and fill the 
			-- the least significant bits with zeros.
			
			-- Trick: if the samples are in binary offset format, just invert the most significant bit.

		--// FRONT-END RECEIVER GAIN CONTROL
		-- When external AGC is enabled, this component can control an external attenuator or 
		-- variable gain amplifier.
		AGC_DAC: out std_logic_vector(11 downto 0);
			-- gain control. May need to be inverted depending on the analog front-end.
			-- Here, maximum AGC_DAC really means minimum gain.
		AGC_DAC_SAMPLE_CLK: out std_logic;
			-- read AGC_DAC at the rising edge of CLK when AGC_DAC_SAMPLE_CLK = 1.
		

		--// CONTROLS 
	   AGC_RESPONSE : IN std_logic_vector(4 downto 0) := "01001";          
			-- Adjust the AGC response time. approximately log2(NSymbols). 
		RECEIVER_CENTER_FREQ: in std_logic_vector(31 downto 0);	
			-- nominal (i.e. expected) center frequency. Expressed as fc/demodulator processing clock * 2^32
			-- This frequency is subtracted from the input signal center frequency. 
			-- Add -fclk/4 when used in conjunction with IF undersampling. 
	   CIC_R: in std_logic_vector(15 downto 0);    
			-- CIC Decimation ratio. The output sampling rate is thus fclk/R
			-- 1 to bypass. 0 is illegal, otherwise, nominal range is 1 to 16384.
			-- Usage: be careful not to decimate too much as the CIC decimation filter is not very sharp and thus
			-- can distort the modulated signal. 
			-- Rule of thumb: the CIC filter output sampling rate should be >= 4 samples per symbol.
		NOMINAL_SYMBOL_RATE: in std_logic_vector(31 downto 0);
			-- = fsymbol rate / fclk * 2^32 = nominal symbol rate
		M_SEL: in std_logic_vector(2 downto 0);
 			-- modulation order M selection 
			-- 0: M=2, 1: M=4, 2: M=8, 3: M=3 SOQPSK precoder
		FILT_SEL: in std_logic_vector(3 downto 0);
			-- filter selection
			-- 0 = FSK
			-- 1 = PCM/FM
			-- 2 = GFSK BT=0.7
			-- 3 = GFSK BT=0.5
			-- 4 = GFSK BT=0.3
			-- 5 = SOQPSK-MIL
			-- 6 = SOQPSK-TG
			-- 7 = multi-h ARTM CPM (Tier 2) 
			-- 8 = GFSK BT=0.25
		MODULATION_INDEX: in std_logic_vector(15 downto 0);
			-- user-specified modulation index. unsigned fixed-point format 4.12
		FRAME_LENGTH: in std_logic_vector(12 downto 0);
			-- frame length in bits. Needed only when sync word detection is enabled (generally SOQPSK)
	   DEMOD_CONTROL: in std_logic_vector(15 downto 0);
			-- bit 0: spectrum inversion enabled(1)/disabled(0)
			-- bit 1: AFC enabled(1)/disabled(0). 
			-- bit 2: freeze AFC  
			-- bit 3: sync word detection enabled (1)/disabled(0)  REQUIRED WITH SOQPSK MODULATIONS
			-- bit 4: FFT enabled(1)/disabled(0) to increase the frequency acquisition range
			
		--// OUTPUT 
		DATA_OUT: out std_logic_vector(3 downto 0);
			-- 4 bit soft-quantized demodulator output
			-- Read at rising edge of CLK when SAMPLE_CLK_OUT = '1';
			-- 4-bit sample format:
			-- 0000 most negative, 1111 most positive, with no zero representation 
		SAMPLE_CLK_OUT: out std_logic;
			-- one CLK-wide pulse
			
		--// Monitoring Information
		AFC_LOCK_OUT: out std_logic;
		CARRIER_LOCK_OUT: out std_logic;
		SIGNAL_PRESENT_OUT: out std_logic;
		CARRIER_FREQUENCY_ERROR: out std_logic_vector(31 downto 0);
            -- Center frequency error: offset with respect to the nominal carrier frequency. 
            -- 32-bit signed integer (2's complement) expressed as cfe * 2^30  / fsymbol rate. 
		POWER_S_AVERAGE_OUT: out std_logic_vector(17 downto 0);
		POWER_N_AVERAGE_OUT: out std_logic_vector(17 downto 0);
			-- averaged on-time signal and noise power. 
			-- Units are irrelevant because of the many AGCs. 
		SNR_LOCKED_OUT: out std_logic_vector(17 downto 0);
			-- SNR when demod is locked. Format 16.2
		BER_SYNC: out std_logic;
			-- BER measurement is synchronized with received PRBS11 test sequence
		BER_ERROR_COUNT: out std_logic_vector(31 downto 0);
			-- BER measurement over the specified window. Valid only when synchronized (BER_SYNC = '1')
			-- with the received PRBS11 test sequence
			-- bit errors expressed in number of BITS
			-- (whereas the window is expressed in bytes)
		BYTE_ERROR: out std_logic;
			-- one pulse for each byte error (helpful in visualizing the bit error distribution with an oscilloscope)
	
		-- COMSCOPE test points
		-- CS0: receiver output I-channel (after open-loop frequency translation to baseband, decimation, lpf, agc)
		-- CS1: I channel after AGC, frequency translation to baseband, resampling at 4 samples/symbol
		-- CS2: symbol tracking loop: accumulated ST phase correction (1 sample/symbol)
		-- CS3: carrier tracking loop: accumulated carrier phase correction (4 samples/symbol)
		-- CS4: multi-symbol detector output (1 sample per bit)
		-- CS5: TBD
		-- CS6: TBD
		-- CS7: TBD
		-- CS8: TBD
		-- CS9: TBD
		-- CS10: TBD
		-- CS11: TBD
		-- T1: TBD
		-- T2: TBD
		CS0: out std_logic_vector(7 downto 0); 
		CS0_CLK: out std_logic;
		CS1: out std_logic_vector(7 downto 0); 
		CS1_CLK: out std_logic;
		CS2: out std_logic_vector(7 downto 0); 
		CS2_CLK: out std_logic;
		CS3: out std_logic_vector(7 downto 0);	
		CS3_CLK: out std_logic;
		CS4: out std_logic_vector(7 downto 0); 
		CS4_CLK: out std_logic;
		CS5: out std_logic_vector(7 downto 0);
		CS5_CLK: out std_logic;
		CS6: out std_logic_vector(7 downto 0);
		CS6_CLK: out std_logic;
		CS7: out std_logic_vector(7 downto 0);
		CS7_CLK: out std_logic;
		CS8: out std_logic_vector(7 downto 0); 
		CS8_CLK: out std_logic;
		CS9: out std_logic_vector(7 downto 0); 
		CS9_CLK: out std_logic;
		CS10: out std_logic_vector(7 downto 0); 
		CS10_CLK: out std_logic;
		CS11: out std_logic_vector(7 downto 0); 
		CS11_CLK: out std_logic;
		T1: out std_logic;	
		T1_CLK: out std_logic;
		T2: out std_logic;	
		T2_CLK: out std_logic;

		TP : OUT std_logic_vector(20 downto 1)

			  );
end entity;

architecture Behavioral of COM1827_RX is
--------------------------------------------------------
--      COMPONENTS
--------------------------------------------------------
	COMPONENT RECEIVER1B
	generic (
		CLK_FREQUENCY: integer;
		SIMULATION: std_logic 
	);
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATA_I_IN : IN std_logic_vector(15 downto 0);
		DATA_Q_IN : IN std_logic_vector(15 downto 0);
		SAMPLE_CLK_IN: IN std_logic;
		CENTER_FREQ : IN std_logic_vector(31 downto 0);
		AGC_RESPONSE : IN std_logic_vector(4 downto 0);
		AGC_INITIAL_GAIN: IN std_logic_vector(11 downto 0); 
	   CIC_R: in std_logic_vector(15 downto 0);    
		CONTROL : IN std_logic_vector(8 downto 0);          
		AGC_DAC : OUT std_logic_vector(11 downto 0);
		AGC_DAC_SAMPLE_CLK : OUT std_logic;
		DATA_I_OUT: out std_logic_vector(13 downto 0);
		DATA_Q_OUT: out std_logic_vector(13 downto 0);
		SAMPLE_CLK_OUT: out std_logic;
		SATURATION: out std_logic;
		TP : OUT std_logic_vector(10 downto 1);
		CS1 : OUT std_logic_vector(7 downto 0);
		CS1_CLK : OUT std_logic;
		CS2 : OUT std_logic_vector(7 downto 0);
		CS2_CLK : OUT std_logic;
		CS3 : OUT std_logic_vector(7 downto 0);
		CS3_CLK : OUT std_logic;
		CS4 : OUT std_logic_vector(7 downto 0);
		CS4_CLK : OUT std_logic
		);
	END COMPONENT;

    COMPONENT DIVIDER
	 Generic(
		NBITS: integer
	 );
    PORT(
         CLK : IN  std_logic;
         NUM : IN  std_logic_vector((NBITS-1) downto 0);
         DENOM : IN  std_logic_vector((NBITS-1) downto 0);
         SAMPLE_CLK_IN : IN  std_logic;
         QUOTIENT : OUT  std_logic_vector((NBITS-1) downto 0);
         REMAINDER : OUT  std_logic_vector((NBITS-1) downto 0);
         SAMPLE_CLK_OUT : OUT  std_logic
        );
    END COMPONENT;

	COMPONENT CPM_DEMOD
	generic (
		SIMULATION: std_logic 
	);
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATA_I_IN: in std_logic_vector(13 downto 0);
		DATA_Q_IN: in std_logic_vector(13 downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		INPUT_SAMPLING_RATE: in std_logic_vector(31 downto 0);
		NOMINAL_SYMBOL_RATE: in std_logic_vector(31 downto 0);
		M_SEL: in std_logic_vector(2 downto 0);
		FILT_SEL: in std_logic_vector(3 downto 0);
		MODULATION_INDEX: in std_logic_vector(15 downto 0);
		FRAME_LENGTH: in std_logic_vector(12 downto 0);
		CONTROL : IN std_logic_vector(15 downto 0);
		DATA_OUT : OUT std_logic_vector(3 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic;
		AFC_LOCK_OUT: out std_logic;
		CARRIER_LOCK_OUT : OUT std_logic;
		SIGNAL_PRESENT_OUT: out std_logic;
		CARRIER_FREQUENCY_ERROR: out std_logic_vector(31 downto 0);
		POWER_OUT : OUT std_logic_vector(13 downto 0);
		TP : OUT std_logic_vector(10 downto 1);
		CS1: out std_logic_vector(7 downto 0);	
		CS1_CLK: out std_logic;
		CS2: out std_logic_vector(7 downto 0);	
		CS2_CLK: out std_logic;
		CS3: out std_logic_vector(7 downto 0);	
		CS3_CLK: out std_logic;
		CS4: out std_logic_vector(7 downto 0);	
		CS4_CLK: out std_logic;
		CS5: out std_logic_vector(7 downto 0);	
		CS5_CLK: out std_logic
		);
	END COMPONENT;

	COMPONENT PX_TO_P8_CONVERSION
	PORT(
		CLK : IN std_logic;
		DATA_IN : IN std_logic_vector(7 downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		WIDTH_IN : IN std_logic_vector(2 downto 0);          
		DATA_OUT : OUT std_logic_vector(7 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic
		);
	END COMPONENT;

	COMPONENT BER2
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATA_IN : IN std_logic_vector(7 downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		CONTROL : IN std_logic_vector(7 downto 0);          
		MF_DETECT : OUT std_logic;
		MF_DETECT_CONFIRMED : OUT std_logic;
		SYNC_LOCK : OUT std_logic;
		BYTE_ERROR : OUT std_logic;
		DATA_REPLICA : OUT std_logic_vector(7 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic;
		BER : OUT std_logic_vector(31 downto 0);
		BER_SAMPLE_CLK : OUT std_logic;
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;

	component SIM2OUTFILE is
		 Generic (
			FILENAME: string
		 );
		 Port ( 
			--// CLK, RESET
			CLK: in std_logic;
				-- Reference clock
			DATA1: in std_logic_vector(11 downto 0);
			DATA2: in std_logic_vector(11 downto 0);
			DATA3: in std_logic_vector(11 downto 0);
			SAMPLE_CLK_IN: in std_logic
				-- DATA_IN is read at the rising edge of CLK when SAMPLE_CLK_IN = '1'

	);
	END COMPONENT;
	
--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
-- Suffix _D indicates a one CLK delayed version of the net with the same name
-- Suffix _X indicates an extended precision version of the net with the same name
-- Suffix _N indicates an inverted version of the net with the same name

--//-- RECLOCK INPUTS ---------------------
signal ADC_DATA_I_IN_D: std_logic_vector(15 downto 0) := (others => '0');
signal ADC_DATA_Q_IN_D: std_logic_vector(15 downto 0) := (others => '0');
signal ADC_SAMPLE_CLK_IN_D: std_logic := '0';

--//-- DIGITAL RECEIVER FRONT-END -------------------------
signal DATA1I: std_logic_vector(13 downto 0) := (others => '0');
signal DATA1Q: std_logic_vector(13 downto 0) := (others => '0');
signal SAMPLE1_CLK: std_logic := '0';
signal RECEIVER1_SATURATION: std_logic := '0';

signal DV_NUM: std_logic_vector(32 downto 0) := (others => '0');
signal DV_DENOM: unsigned(32 downto 0) := (others => '0');
signal INPUT_SAMPLING_RATE: std_logic_vector(32 downto 0) := (others => '0');

--//-- DEMODULATOR --------------------------------------------
signal SYMBOL_CLK: std_logic := '0';	-- misnomer: chip clk
signal DATA_OUT_local: std_logic_vector(3 downto 0) := (others => '0');
signal SAMPLE_CLK_OUT_local: std_logic := '0';
signal ANALOG_DEMOD_SYMBOL_CLK_OUT: std_logic := '0';
signal ANALOG_DEMOD_I_OUT: std_logic_vector(17 downto 0) := (others => '0');
signal ANALOG_DEMOD_Q_OUT: std_logic_vector(17 downto 0) := (others => '0');
signal CPM_DEMOD_TP: std_logic_vector(10 downto 1) := (others => '0');

--//-- BER MEASUREMENT  ---------------------------------------------------------
signal RX_DATA1b1_X: std_logic_vector(7 downto 0) := (others => '0');
signal RX_SAMPLE1b1_CLK: std_logic := '0';
signal RX_DATA8b1: std_logic_vector(7 downto 0) := (others => '0');
signal RX_SAMPLE8b1_CLK: std_logic := '0';
signal BER_CONTROL: std_logic_vector(7 downto 0) := (others => '0');
signal BER_MF_DETECT: std_logic := '0';
signal BER_MF_DETECT_CONFIRMED: std_logic := '0';
--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
begin

--// RECLOCK INPUTS ---------------------
-- Immediately reclock inputs for best timing.
RECLOCK_IN_001: process(CLK)
begin
	if rising_edge(CLK) then
		ADC_SAMPLE_CLK_IN_D <= ADC_SAMPLE_CLK_IN;
		ADC_DATA_I_IN_D <= ADC_DATA_I_IN;
		ADC_DATA_Q_IN_D <= ADC_DATA_Q_IN;
	end if;
end process;

--//-- DIGITAL RECEIVER FRONT-END -------------------------
-- Includes AGC, frequency translation to baseband, decimation and LPF.
RECEIVER1_001: RECEIVER1B 
GENERIC MAP(
	CLK_FREQUENCY => 160,
	SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK,
	SYNC_RESET => SYNC_RESET,
	DATA_I_IN => ADC_DATA_I_IN_D,
	DATA_Q_IN => ADC_DATA_Q_IN_D,	-- IF undersampling. Force Q to zero
	SAMPLE_CLK_IN => ADC_SAMPLE_CLK_IN_D,
	AGC_DAC => AGC_DAC,
	AGC_DAC_SAMPLE_CLK => AGC_DAC_SAMPLE_CLK,
	AGC_RESPONSE => AGC_RESPONSE,
	AGC_INITIAL_GAIN => x"800",	-- mid range
	CENTER_FREQ => RECEIVER_CENTER_FREQ,
	CIC_R => CIC_R,	
	CONTROL => "000000010",	-- enable both internal/external AGCs
	DATA_I_OUT => DATA1I,
	DATA_Q_OUT => DATA1Q,
	SAMPLE_CLK_OUT => SAMPLE1_CLK,
	SATURATION => RECEIVER1_SATURATION,
	TP => open,
	CS1 => open,
	CS1_CLK => open,
	CS2 => open,
	CS2_CLK => open,
	CS3 => open,
	CS3_CLK => open,
	CS4 => open,
	CS4_CLK => open
);

-- estimates the SAMPLE1_CLK sampling rate at the RECEIVER1B output (needed in CPM_DEMOD resampling)
DV_NUM <= '1' & x"00000000";
DV_DENOM <= resize(unsigned(CIC_R),33);
DIVIDER_002: DIVIDER 
GENERIC MAP(
	NBITS => 33
)
PORT MAP (
	 CLK => CLK,
	 NUM => DV_NUM,
	 DENOM => std_logic_vector(DV_DENOM),
	 SAMPLE_CLK_IN => SYNC_RESET,
	 QUOTIENT => INPUT_SAMPLING_RATE,
	 REMAINDER => open,
	 SAMPLE_CLK_OUT => open
  );

--//-- DEMODULATOR --------------------------------------------
CPM_DEMOD_001: CPM_DEMOD 
GENERIC MAP(
	SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK,
	SYNC_RESET => SYNC_RESET,	
	DATA_I_IN => DATA1I,	
	DATA_Q_IN => DATA1Q,	
	SAMPLE_CLK_IN => SAMPLE1_CLK,
	INPUT_SAMPLING_RATE => INPUT_SAMPLING_RATE(31 downto 0),
	NOMINAL_SYMBOL_RATE => NOMINAL_SYMBOL_RATE,
	M_SEL => M_SEL,
	FILT_SEL => FILT_SEL,
	MODULATION_INDEX => MODULATION_INDEX,
	FRAME_LENGTH => FRAME_LENGTH,
	CONTROL => DEMOD_CONTROL,
	DATA_OUT => DATA_OUT_local,
	SAMPLE_CLK_OUT => SAMPLE_CLK_OUT_local,
	AFC_LOCK_OUT => AFC_LOCK_OUT,
	CARRIER_LOCK_OUT => CARRIER_LOCK_OUT,
	SIGNAL_PRESENT_OUT => SIGNAL_PRESENT_OUT,
	CARRIER_FREQUENCY_ERROR => CARRIER_FREQUENCY_ERROR,
	POWER_OUT => open,
	TP => CPM_DEMOD_TP,
	CS1 => CS1,
	CS1_CLK => CS1_CLK,
	CS2 => CS2,
	CS2_CLK => CS2_CLK,
	CS3 => CS3,
	CS3_CLK => CS3_CLK,
	CS4 => CS4,
	CS4_CLK => CS4_CLK,
	CS5 => CS5,
	CS5_CLK => CS5_CLK
);

-- 1-bit serial to 8-bit parallel conversion
RX_DATA1b1_X <= (0 => DATA_OUT_local(3), others => '0');
RX_SAMPLE1b1_CLK <= SAMPLE_CLK_OUT_local;
PX_TO_P8_CONVERSION_003: PX_TO_P8_CONVERSION 
PORT MAP(
	CLK => CLK,
	DATA_IN => RX_DATA1b1_X,		-- 1-bit serial input
	SAMPLE_CLK_IN => RX_SAMPLE1b1_CLK,
	WIDTH_IN => "001",
	DATA_OUT => RX_DATA8b1,		-- 8-bit parallel output
	SAMPLE_CLK_OUT => RX_SAMPLE8b1_CLK
);

-- to output
-- select output format:
-- bit 9: Output format (0) 8 demodulated bits packed in a byte, hard-quantized (1) 4-bit soft-quantized, .
OUTPUT_FORMAT_001: process(CLK)
begin
    if rising_edge(CLK) then
		-- Output format (1) 4-bit soft-quantized
		DATA_OUT <= DATA_OUT_local;
		SAMPLE_CLK_OUT <= SAMPLE_CLK_OUT_local;
    end if;
end process;

--//-- BER MEASUREMENT  ---------------------------------------------------------
BER2_001: if(BER_EN = '1') generate
	-- Measure BER when a PRSB-11 test sequence is transmitted
	BER_CONTROL(2 downto 0) <= "000"; -- BER measured over 1,000-byte window.
--	BER_CONTROL(2 downto 0) <= "001"; -- BER measured over 10,000-byte window.
	BER_CONTROL(7 downto 3) <= (others => '0'); -- unused
	
	BER2_001: BER2 PORT MAP(
		CLK => CLK,
		SYNC_RESET => SYNC_RESET,
		DATA_IN => RX_DATA8b1,
		SAMPLE_CLK_IN => RX_SAMPLE8b1_CLK,
		CONTROL => BER_CONTROL,
		MF_DETECT => BER_MF_DETECT,
		MF_DETECT_CONFIRMED => BER_MF_DETECT_CONFIRMED,
		SYNC_LOCK => BER_SYNC,
		BYTE_ERROR => BYTE_ERROR,
		DATA_REPLICA => open,
		SAMPLE_CLK_OUT => open,
		BER => BER_ERROR_COUNT,
		BER_SAMPLE_CLK => open,
		TP => open
	);
end generate;


--// SIM2OUTFILE --------------------------------------------
-- simulation. send to a tab-delimited text file for subsequent (Matlab) plot.
--
SIM2OUTFILE_X: if(SIMULATION = '1') generate
--	SIM2OUTFILE_001: SIM2OUTFILE 
--	generic map(
--		FILENAME => "rx_top1.txt"
--	)
--	PORT MAP(
--		CLK => CLK,
--		DATA1 => DATA1I(13 downto 2),	-- receiver1 output I,
--		DATA2 => DATA1Q(13 downto 2),	-- receiver1 output Q,
--		DATA3 => x"000",
--		SAMPLE_CLK_IN => SAMPLE1_CLK
--	);
--
end generate;

--// MONITORING, TEST POINTS --------------------------------------------
CS0 <= DATA1I(13 downto 6);
CS0_CLK <= SAMPLE1_CLK;
TP(10 downto 1) <= CPM_DEMOD_TP;
TP(20) <= RECEIVER1_SATURATION;
end Behavioral;
