-------------------------------------------------------------
--	Filename:  CLKDOUBLER_DCM.VHD
-- Authors: 
--		Alain Zarembowitch / MSS, 
--	Version: 1
--	Date last modified: 9-27-10
-- Inheritance: 	none
--
-- description: frequency doubler
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;

entity CLKDOUBLER_DCM is
port
 (-- Clock in ports (directly from input pin)
  CLK_REF_IN      : in     std_logic;
  ASYNC_RESET 		: in std_logic;
  -- Clock out ports (after BUFGs)
  CLKx2G          : out    std_logic;
  CLKx2_180G      : out    std_logic;
  -- Status and control signals
  LOCKED_DCM      : out    std_logic
 );
end entity;

architecture Behavioral of CLKDOUBLER_DCM is
--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
signal CLKx2: std_logic;
signal CLKx2_180: std_logic;
signal CLKx2G_LOCAL: std_logic;

--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
begin

   -- DCM_SP: Digital Clock Manager
   --         Spartan-6
   -- Xilinx HDL Language Template, version 11.4

   DCM_SP_inst : DCM_SP
   generic map (
      CLKDV_DIVIDE => 2.0,                   -- CLKDV divide value
                                             -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
      CLKFX_DIVIDE => 1,                     -- Divide value - D - (1-32)
      CLKFX_MULTIPLY => 2,                   -- Multiply value - M - (2-32)
      CLKIN_DIVIDE_BY_2 => FALSE,            -- CLKIN divide by two (TRUE/FALSE)
      CLKIN_PERIOD => 7.7,                	-- Input clock period specified in nS
      CLKOUT_PHASE_SHIFT => "NONE",          -- Output phase shift (NONE, FIXED, VARIABLE)
      CLK_FEEDBACK => "2X",                  -- Feedback source (NONE, 1X, 2X)
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
      DFS_FREQUENCY_MODE => "LOW",           -- Unsupported - Do not change value
      DLL_FREQUENCY_MODE => "LOW",           -- Unsupported - Do not change value
      DSS_MODE => "NONE",                    -- Unsupported - Do not change value
      DUTY_CYCLE_CORRECTION => TRUE,         -- Unsupported - Do not change value
      FACTORY_JF => X"c080",                 -- Unsupported - Do not change value
      PHASE_SHIFT => 0,                      -- Amount of fixed phase shift (-255 to 255)
      STARTUP_WAIT => FALSE                  -- Delay config DONE until DCM LOCKED (TRUE/FALSE)
   )
   port map (
      CLK0 => open,         		-- 1-bit 0 degree clock output
      CLK90 => open,      			-- 1-bit 90 degree clock output
      CLK180 => open,    			-- 1-bit 180 degree clock output
      CLK270 => open,    			-- 1-bit 270 degree clock output
      CLK2X => CLKx2,       		-- 1-bit 2X clock frequency clock output
      CLK2X180 => CLKx2_180, 		-- 1-bit 2X clock frequency, 180 degree clock output
      CLKDV => open,       		-- 1-bit Divided clock output
      CLKFX => open,       		-- 1-bit Digital Frequency Synthesizer output (DFS)
      CLKFX180 => open, 			-- 1-bit 180 degree CLKFX output
      LOCKED => LOCKED_DCM,     	-- 1-bit DCM Lock Output
      PSDONE => open,     			-- 1-bit Phase shift done output
      STATUS => open,     			-- 8-bit DCM status output
      CLKFB => CLKx2G_LOCAL,      -- 1-bit Clock feedback input
      CLKIN => CLK_REF_IN,     	-- 1-bit Clock input from PLL above
      DSSEN => '0',       			-- 1-bit Unsupported
      PSCLK => '0',       			-- 1-bit Phase shift clock input
      PSEN => '0',         		-- 1-bit Phase shift enable
      PSINCDEC => '0', 				-- 1-bit Phase shift increment/decrement input
      RST => ASYNC_RESET         -- 1-bit Active high reset input
   );

  -- Output buffering
  -------------------------------------
BUFG_002: BUFG port map(I => CLKx2, O => CLKx2G_LOCAL);
BUFG_003: BUFG port map(I => CLKx2_180, O => CLKx2_180G);
CLKx2G <= CLKx2G_LOCAL;

end Behavioral;
