--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:47:36 11/21/2011
-- Design Name:   
-- Module Name:   C:/Users/Alain/Documents/source_VHDL/com-1504WHOI/com-1504_000/src/COM3504/tbaux_dacs_adc.vhd
-- Project Name:  com1504_ise131
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: AUX_DACS_ADC
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tbaux_dacs_adc IS
END tbaux_dacs_adc;
 
ARCHITECTURE behavior OF tbaux_dacs_adc IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT AUX_DACS_ADC
	generic (
		CLK_FREQUENCY: integer 
	);
    PORT(
         CLK : IN  std_logic;
         ASYNC_RESET : IN  std_logic;
         AUXDAC1_DIN : IN  std_logic_vector(11 downto 0);
         AUXDAC2_DIN : IN  std_logic_vector(11 downto 0);
         AUXADC1_DOUT : OUT  std_logic_vector(11 downto 0);
			TIMESLOTS_AUXDAC1: in std_logic_vector(15 downto 0);
			TIMESLOTS_AUXDAC2: in std_logic_vector(15 downto 0);
			TIMESLOTS_AUXADC1: in std_logic_vector(15 downto 0);
         AUX_SPI1 : INOUT  std_logic;
         AUX_SPI2 : OUT  std_logic;
         AUX_SPI3 : OUT  std_logic;
         AUX_SPI4 : OUT  std_logic;
         AUX_SPI5 : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal ASYNC_RESET : std_logic := '0';
   signal AUXDAC1_DIN : std_logic_vector(11 downto 0) := (others => '0');
   signal AUXDAC2_DIN : std_logic_vector(11 downto 0) := (others => '0');

	--BiDirs
   signal AUX_SPI1 : std_logic :='Z';

 	--Outputs
   signal AUXADC1_DOUT : std_logic_vector(11 downto 0);
   signal AUX_SPI2 : std_logic;
   signal AUX_SPI3 : std_logic;
   signal AUX_SPI4 : std_logic;
   signal AUX_SPI5 : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 8 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: AUX_DACS_ADC 
	GENERIC MAP(
		CLK_FREQUENCY => 60
	)
	PORT MAP (
          CLK => CLK,
          ASYNC_RESET => ASYNC_RESET,
          AUXDAC1_DIN => AUXDAC1_DIN,
          AUXDAC2_DIN => AUXDAC2_DIN,
          AUXADC1_DOUT => AUXADC1_DOUT,
			 TIMESLOTS_AUXDAC1 => x"FEFE",
			 TIMESLOTS_AUXDAC2 => x"0001",
			 TIMESLOTS_AUXADC1 => x"0100",
          AUX_SPI1 => AUX_SPI1,
          AUX_SPI2 => AUX_SPI2,
          AUX_SPI3 => AUX_SPI3,
          AUX_SPI4 => AUX_SPI4,
          AUX_SPI5 => AUX_SPI5
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
	ASYNC_RESET <= '0';
	AUXDAC1_DIN <= x"123";
	AUXDAC2_DIN <= x"456";

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for CLK_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
