Release 8.2i Map I.31
Xilinx Mapping Report File for Design 'BER_GEN'

Design Information
------------------
Command Line   : C:\Xilinx\bin\nt\map.exe -ise
C:/VHDL/com-1023_014/COM1023_ISE82.ise -intstyle ise -p xc2s200-pq208-6 -cm area
-pr b -k 4 -c 100 -tx off -o BER_GEN_map.ncd BER_GEN.ngd BER_GEN.pcf 
Target Device  : xc2s200
Target Package : pq208
Target Speed   : -6
Mapper Version : spartan2 -- $Revision: 1.34.32.1 $
Mapped Date    : Wed Sep 02 14:52:39 2009

Design Summary
--------------
Number of errors:      0
Number of warnings:   25
Logic Utilization:
  Number of Slice Flip Flops:     1,621 out of  4,704   34%
  Number of 4 input LUTs:         2,483 out of  4,704   52%
Logic Distribution:
    Number of occupied Slices:                       1,694 out of  2,352   72%
    Number of Slices containing only related logic:  1,694 out of  1,694  100%
    Number of Slices containing unrelated logic:         0 out of  1,694    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        2,683 out of  4,704   57%
      Number used as logic:                     2,483
      Number used as a route-thru:                200
   Number of bonded IOBs:            98 out of    140   70%
      IOB Flip Flops:                              30
   Number of Block RAMs:              5 out of     14   35%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  117,529
Additional JTAG gate count for IOBs:  4,752
Peak Memory Usage:  162 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network CLK_IN1 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 24
   more times for the following (max. 5 shown):
   CONTROL<7>,
   CONTROL<6>,
   CONTROL<5>,
   CONTROL<4>,
   CONTROL<3>
   To see the details of these warning messages, please use the -detail switch.
WARNING:MapLib:96 - IBUF symbol "IBUF_003" (output signal=UC_WRN_INB) driving
   BUFG is LOCed to a generic IOB site. This will cause lower performance than
   using a dedicated GCLKIOB site.
WARNING:MapLib:96 - IBUF symbol "IBUF_004" (output signal=UC_ALE_INB) driving
   BUFG is LOCed to a generic IOB site. This will cause lower performance than
   using a dedicated GCLKIOB site.
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	Mmult_DATA2_I_ABS_Madd5_cy<5>
   	Mmult_DATA2_I_ABS_Madd5_cy<6>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	Mmult_DATA2_Q_ABS_Madd1_cy<14>
   	Mmult_DATA2_Q_ABS_Madd1_cy<15>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	Mmult_DATA2_Q_ABS_Madd5_cy<5>
   	Mmult_DATA2_Q_ABS_Madd5_cy<6>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	Mmult_DATA2_I_ABS_Madd_cy<13>
   	Mmult_DATA2_I_ABS_Madd_cy<14>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	PM_002_Mmult_DATA_SQUARE_Madd1_cy<18>
   	PM_002_Mmult_DATA_SQUARE_Madd1_cy<19>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	Mmult_DATA2_Q_ABS_Madd_cy<13>
   	Mmult_DATA2_Q_ABS_Madd_cy<14>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	PM_001_Mmult_DATA_SQUARE_Madd1_cy<18>
   	PM_001_Mmult_DATA_SQUARE_Madd1_cy<19>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	PM_001_Mmult_DATA_SQUARE_Madd3_cy<15>
   	PM_001_Mmult_DATA_SQUARE_Madd3_cy<16>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	PM_001_Mmult_DATA_SQUARE_Madd3_cy<18>
   	PM_001_Mmult_DATA_SQUARE_Madd3_cy<19>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	PM_001_Mmult_DATA_SQUARE_Madd3_cy<19>
   	PM_001_Mmult_DATA_SQUARE_Madd3_cy<20>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	Mmult_DATA3B_ABS_Madd5_cy<5>
   	Mmult_DATA3B_ABS_Madd5_cy<6>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	Mmult_DATA3A_ABS_Madd5_cy<5>
   	Mmult_DATA3A_ABS_Madd5_cy<6>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	BIT_ERROR_Mcount_COUNT_cy<0>
   	BIT_ERROR_Mcount_COUNT_cy<1>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	Mmult_DATA2_I_ABS_Madd1_cy<14>
   	Mmult_DATA2_I_ABS_Madd1_cy<15>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	AWGN_GEN_001_Mmult_N1_Madd5_cy<5>
   	AWGN_GEN_001_Mmult_N1_Madd5_cy<6>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
   	PM_002_Mmult_DATA_SQUARE_Madd_cy<16>
   	PM_002_Mmult_DATA_SQUARE_Madd_cy<17>
WARNING:PhysDesignRules:1109 - Blockcheck: Dangling BLOCKRAM_BLOCKRAMA output.
   Pin OUT11 of comp AWGN_GEN_001_RAMB4_S16_001/AWGN_GEN_001_RAMB4_S16_001.A is
   not connected.
WARNING:PhysDesignRules:1109 - Blockcheck: Dangling BLOCKRAM_BLOCKRAMA output.
   Pin OUT12 of comp AWGN_GEN_001_RAMB4_S16_001/AWGN_GEN_001_RAMB4_S16_001.A is
   not connected.
WARNING:PhysDesignRules:1109 - Blockcheck: Dangling BLOCKRAM_BLOCKRAMA output.
   Pin OUT13 of comp AWGN_GEN_001_RAMB4_S16_001/AWGN_GEN_001_RAMB4_S16_001.A is
   not connected.
WARNING:PhysDesignRules:1109 - Blockcheck: Dangling BLOCKRAM_BLOCKRAMA output.
   Pin OUT14 of comp AWGN_GEN_001_RAMB4_S16_001/AWGN_GEN_001_RAMB4_S16_001.A is
   not connected.
WARNING:PhysDesignRules:1109 - Blockcheck: Dangling BLOCKRAM_BLOCKRAMA output.
   Pin OUT15 of comp AWGN_GEN_001_RAMB4_S16_001/AWGN_GEN_001_RAMB4_S16_001.A is
   not connected.

Section 3 - Informational
-------------------------
INFO:MapLib:564 - The following environment variables are currently set:
INFO:MapLib:591 - XIL_MAP_ALLOW_ANY_DLL_INPUT 	Value: yes

Section 4 - Removed Logic Summary
---------------------------------
   3 block(s) removed
   7 block(s) optimized away
   3 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "PM_001_POWER_ACC_0_rt" is unused and has been removed.
 Unused block "PM_001_POWER_ACC_0_rt" (ROM) removed.
The signal "SIGNAL_SCALING_D_6_1" is unused and has been removed.
 Unused block "SIGNAL_SCALING_D_6_1" (FF) removed.
The signal "SIGNAL_SCALING_D_7_1" is unused and has been removed.
 Unused block "SIGNAL_SCALING_D_7_1" (FF) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC
MUXCY 		Mmult_DATA2_I_ABS_Madd4_cy<6>
MUXCY 		Mmult_DATA2_Q_ABS_Madd4_cy<6>
MUXCY 		PM_001_Madd__addsub0000_cy<0>
MUXCY 		PM_001_Mmult_DATA_SQUARE_Madd4_cy<8>
MUXCY 		PM_001_Mmult_DATA_SQUARE_Madd5_cy<12>

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| CLK_IN2                            | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| J2<2>                              | IOB     | INPUT     | LVTTL       |          |      | INFF     | PULLUP   | IFD   |
| J2<3>                              | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<4>                              | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<5>                              | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<6>                              | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<7>                              | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<8>                              | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<9>                              | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<11>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<12>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<13>                             | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| J2<14>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<15>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<16>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<17>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<18>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<19>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<21>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<22>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<23>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<24>                             | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | IFD   |
| J2<27>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | FAST |          |          |       |
| J3<2>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| J3<3>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| J3<4>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<5>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| J3<6>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<7>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| J3<8>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<9>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| J3<11>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<12>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<13>                             | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          | PULLUP   |       |
| J3<14>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<15>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<16>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<17>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<18>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<19>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<21>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<22>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<23>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<24>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<25>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J3<27>                             | IOB     | INPUT     | LVTTL       |          |      |          | PULLUP   |       |
| J4<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | FAST |          |          |       |
| J4<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<3>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<4>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<5>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<6>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<7>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<8>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<9>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<11>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<12>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<13>                             | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          | PULLUP   |       |
| J4<14>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<15>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<16>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<17>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<18>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<19>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<21>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<22>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<23>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<24>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<25>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| J4<27>                             | IOB     | INPUT     | LVTTL       |          |      |          | PULLUP   |       |
| RX_B                               | IOB     | INPUT     | LVTTL       |          |      |          | PULLUP   |       |
| RX_L                               | IOB     | INPUT     | LVTTL       |          |      |          | PULLUP   |       |
| RX_R                               | IOB     | INPUT     | LVTTL       |          |      |          | PULLUP   |       |
| TP<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TP<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TP<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TP<3>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TP<4>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TP<5>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TP<6>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TP<7>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TP<8>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TP<9>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TX_B                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TX_L                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| TX_R                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| UC_AD<0>                           | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| UC_AD<1>                           | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| UC_AD<2>                           | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| UC_AD<3>                           | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| UC_AD<4>                           | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| UC_AD<5>                           | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| UC_AD<6>                           | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| UC_AD<7>                           | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| UC_ALE_IN                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| UC_FLASH_CSN                       | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| UC_RDN                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| UC_WRN_IN                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
No timing report for this architecture.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
