-------------------------------------------------------------
-- Filename:  COM1600.VHD
-- Authors: 
--		Alain Zarembowitch / MSS
-- Version: Rev 0
-- Last modified: 11/18/11
-- Inheritance: 	n/a
--
-- description:  COM-1600 project to test the GMII PHY interface 

---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

entity COM1600 is
    Port ( 
		--GLOBAL CLOCKS
	   USB_CLK60 : in std_logic;	
			-- 60 MHz reference clock. Generated by the USB PHY on this board.
		EXT_FREQ_REF: in std_logic;
			-- external (higher-stability) frequency reference via J9 SMA connector ("EXT REF")

		--// Left connector, 98 pin PCIe female connector. 
		-- Pins B5,B20,B31,B42 reserved for Ground
		-- Pins A49/B49 reserved for ComBlock Monitoring and Control.
		-- Place B13 in high-impedance when using the 12-bit DAC or vice versa.
		LEFT_CONNECTOR_A: inout std_logic_vector(48 downto 1);
		LEFT_CONNECTOR_B: inout std_logic_vector(48 downto 1);

		--// Right connector: 98 pin PCIe female connector.   
		-- Pins B5,B20,B31,B42 reserved for Ground
		-- Pins A49/B49 reserved for ComBlock Monitoring and Control.
		-- Connector pins A39 - A48, B40,B41,B43-B48 can be used by 
		-- re-routing LEFT_CONNECTOR signals using a resistor array (requires soldering)
		-- See schematics for details.
		RIGHT_CONNECTOR_A: inout std_logic_vector(48 downto 1);
		RIGHT_CONNECTOR_B: inout std_logic_vector(48 downto 1);

		--// DDR2 SDRAM interface
		SDRAM_CK_P: out std_logic;
		SDRAM_CK_N: out std_logic;
		SDRAM_CKE: out std_logic;
		SDRAM_CASN: out std_logic;
		SDRAM_RASN: out std_logic;
		SDRAM_WEN: out std_logic;
		SDRAM_DQS_P: inout std_logic_vector(1 downto 0);
		SDRAM_DQS_N: inout std_logic_vector(1 downto 0);
			-- Bi-directional data strobe lines (differential)
			-- Be sure to enable PULLDOWN on _P and PULLUP on _N to prevent erratic sampling clock.
		SDRAM_DM: out std_logic_vector(1 downto 0);
		SDRAM_DQ: inout std_logic_vector(15 downto 0);
		SDRAM_ODT: out std_logic;
		SDRAM_A: out std_logic_vector(12 downto 0);
		SDRAM_BA: out std_logic_vector(2 downto 0);
		
		--// USB PHY interface (SMSC GT3300 IC)
		-- Direct connection between the USB20ULPI component and the USB PHY.
		-- Synchronous with USB_CLK60G clock
		USB_ULPI_DATA: inout std_logic_vector(7 downto 0);
		USB_ULPI_STP: out std_logic;
		USB_ULPI_NXT: in std_logic;
		USB_ULPI_DIR: in std_logic;
	
		--// Monitoring & Control: ARM Cortex M3 microcontroller interface
		-- asynchronous bus (shared with NAND flash)
		-- set address at the rising edge of UC_WEB_IN when UC_CSIB_IN = '0' and UC_ALE_IN = '1'
		-- write data the rising edge of UC_WEB_IN when UC_CSIB_IN = '0'
		-- read data when  UC_CSIB_IN = '0' and UC_REB_IN = '0'
		UC_CSIB_IN: in std_logic;  -- chip select. active low.
		UC_ALE_IN: in std_logic;  -- address latch enable. active high.
		UC_REB_IN: in std_logic;  -- read enable #
		UC_WEB_IN: in std_logic;	-- write enable #
		UC_AD: inout std_logic_vector(7 downto 0)  -- shared address/data bus

		  
			  );
end entity;

architecture Behavioral of COM1600 is
--------------------------------------------------------
--      COMPONENTS
--------------------------------------------------------
-- TODO: comment out unused components/drivers
	COMPONENT CLKGEN_PLL
	PORT(
		CLKREF_IN : IN std_logic;
		CLKOUT0G : OUT std_logic;
		CLKOUT1G : OUT std_logic;
		CLKOUT2G : OUT std_logic;
		LOCKED_PLL : OUT std_logic
		);
	END COMPONENT;

	COMPONENT COM5401
	GENERIC (
		MII_SEL: std_logic;  
		PHY_ADDR: std_logic_vector(4 downto 0);
		CLK_FREQUENCY: integer 
	);
	PORT(
		CLK : IN std_logic;
		ASYNC_RESET : IN std_logic;
		MAC_TX_CONFIG : IN std_logic_vector(15 downto 0);
		MAC_RX_CONFIG : IN std_logic_vector(15 downto 0);
		MAC_ADDR : IN std_logic_vector(47 downto 0);
		PHY_CONFIG_CHANGE : IN std_logic;
		PHY_RESET : IN std_logic;
		SPEED : IN std_logic_vector(1 downto 0);
		DUPLEX : IN std_logic;
		TEST_MODE : IN std_logic_vector(1 downto 0);
		POWER_DOWN : IN std_logic;
		CLK_SKEW : IN std_logic_vector(15 downto 0);
		MAC_TX_DATA : IN std_logic_vector(7 downto 0);
		MAC_TX_DATA_VALID : IN std_logic;
		MAC_TX_EOF : IN std_logic;
		MAC_RX_CTS : IN std_logic;
		RXC : IN std_logic;
		RXD : IN std_logic_vector(3 downto 0);
		RX_CTL : IN std_logic;
		MII_TX_CLK : IN std_logic;
		GMII_MII_CRS : IN std_logic;
		GMII_MII_COL : IN std_logic;
		GMII_MII_RX_CLK : IN std_logic;
		GMII_MII_RXD : IN std_logic_vector(7 downto 0);
		GMII_MII_RX_DV : IN std_logic;
		GMII_MII_RX_ER : IN std_logic;    
		MDIO : INOUT std_logic;      
		MAC_TX_CTS : OUT std_logic;
		MAC_RX_DATA : OUT std_logic_vector(7 downto 0);
		MAC_RX_DATA_VALID : OUT std_logic;
		MAC_RX_SOF : OUT std_logic;
		MAC_RX_EOF : OUT std_logic;
		TXC : OUT std_logic;
		TXD : OUT std_logic_vector(3 downto 0);
		TX_CTL : OUT std_logic;
		RESET_N : OUT std_logic;
		MCLK : OUT std_logic;
		GMII_TX_CLK : OUT std_logic;
		GMII_MII_TXD : OUT std_logic_vector(7 downto 0);
		GMII_MII_TX_EN : OUT std_logic;
		GMII_MII_TX_ER : OUT std_logic;
		LINK_STATUS : OUT std_logic;
		SPEED_STATUS : OUT std_logic_vector(1 downto 0);
		DUPLEX_STATUS : OUT std_logic;
		PHY_ID: out std_logic_vector(15 downto 0);
		CS_CLKG: out std_logic;	-- synchronous clock for the comscope traces
		CS1: out std_logic_vector(7 downto 0);
		CS1_CLK: out std_logic;
		CS2: out std_logic_vector(7 downto 0);
		CS2_CLK: out std_logic;
		TP: out std_logic_vector(10 downto 1)
		);
	END COMPONENT;

	COMPONENT LAN_TX_TEST
	PORT(
		CLK : IN std_logic;
		ASYNC_RESET : IN std_logic;
		MAC_TX_CTS : IN std_logic;          
		MAC_TX_DATA : OUT std_logic_vector(7 downto 0);
		MAC_TX_DATA_VALID : OUT std_logic;
		MAC_TX_EOF : OUT std_logic
		);
	END COMPONENT;

	COMPONENT USB20ULPI
	PORT(
		SYNC_RESET : IN std_logic;
		USB_CLK60G : IN std_logic;
		CLK_P : IN std_logic;
		USB_ULPI_NXT : IN std_logic;
		USB_ULPI_DIR : IN std_logic;
		DATA1_OUT_SAMPLE_CLK_REQ : IN std_logic;
		DATA1_IN : IN std_logic_vector(7 downto 0);
		DATA1_IN_SAMPLE_CLK : IN std_logic;
		DATA2_OUT_SAMPLE_CLK_REQ : IN std_logic;
		DATA2_IN : IN std_logic_vector(7 downto 0);
		DATA2_IN_SAMPLE_CLK : IN std_logic;    
		USB_ULPI_DATA : INOUT std_logic_vector(7 downto 0);      
		USB_ULPI_STP : OUT std_logic;
		DATA1_OUT : OUT std_logic_vector(7 downto 0);
		DATA1_OUT_SAMPLE_CLK : OUT std_logic;
		DATA1_OUT_BUFFER_EMPTY : OUT std_logic;
		DATA1_IN_SAMPLE_CLK_REQ : OUT std_logic;
		DATA2_OUT : OUT std_logic_vector(7 downto 0);
		DATA2_OUT_SAMPLE_CLK : OUT std_logic;
		DATA2_OUT_BUFFER_EMPTY : OUT std_logic;
		DATA2_IN_SAMPLE_CLK_REQ : OUT std_logic;
		PHY_VENDOR_ID : OUT std_logic_vector(7 downto 0);
		CS1 : OUT std_logic_vector(7 downto 0);
		CS1_CLK : OUT std_logic;
		CS2 : OUT std_logic_vector(7 downto 0);
		CS2_CLK : OUT std_logic;
		CS3 : OUT std_logic_vector(7 downto 0);
		CS3_CLK : OUT std_logic;
		T1 : OUT std_logic;
		T1_CLK : OUT std_logic;
		T2 : OUT std_logic;
		T2_CLK : OUT std_logic;
		USB_TP : OUT std_logic_vector(20 downto 1)
		);
	END COMPONENT;



	COMPONENT COMSCOPE
	GENERIC (
		-- select features as needed: number of traces, widths
		-- One must re-synthesize after changing these choices.
		-- enable individual traces. '1' for enable, '0' for disable
		TRACE1_ENABLED: std_logic;	
		TRACE2_ENABLED: std_logic;	
		TRACE3_ENABLED: std_logic;	
		TRACE4_ENABLED: std_logic
	);	
	PORT(
		CLK : IN std_logic;
		ASYNC_RESET : IN std_logic;
		SIGNED_REPRESENTATION_U_SIGNED_N : IN std_logic;
		REG237 : IN std_logic_vector(7 downto 0);
		REG238 : IN std_logic_vector(7 downto 0);
		REG239 : IN std_logic_vector(7 downto 0);
		REG240 : IN std_logic_vector(7 downto 0);
		REG241 : IN std_logic_vector(7 downto 0);
		REG242 : IN std_logic_vector(7 downto 0);
		REG243 : IN std_logic_vector(7 downto 0);
		REG244 : IN std_logic_vector(7 downto 0);
		REG245 : IN std_logic_vector(7 downto 0);
		REG246 : IN std_logic_vector(7 downto 0);
		REG247 : IN std_logic_vector(7 downto 0);
		REG248 : IN std_logic_vector(7 downto 0);
		REG249 : IN std_logic_vector(7 downto 0);
		SIGNAL_1_BIT_1_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_1_BIT_1_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_1_BIT_1_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_1_BIT_1_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_2_BIT_1_1 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_2_BIT_1_2 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_2_BIT_1_3 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_2_BIT_1_4 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_4_BIT_1_1 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_4_BIT_1_2 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_4_BIT_1_3 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_4_BIT_1_4 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_8_BIT_1_1 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_8_BIT_1_2 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_8_BIT_1_3 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_8_BIT_1_4 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_16_BIT_1_1 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_16_BIT_1_2 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_16_BIT_1_3 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_16_BIT_1_4 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_1_BIT_2_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_1_BIT_2_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_1_BIT_2_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_1_BIT_2_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_2_BIT_2_1 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_2_BIT_2_2 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_2_BIT_2_3 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_2_BIT_2_4 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_4_BIT_2_1 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_4_BIT_2_2 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_4_BIT_2_3 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_4_BIT_2_4 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_8_BIT_2_1 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_8_BIT_2_2 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_8_BIT_2_3 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_8_BIT_2_4 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_16_BIT_2_1 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_16_BIT_2_2 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_16_BIT_2_3 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_16_BIT_2_4 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_1_BIT_3_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_1_BIT_3_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_1_BIT_3_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_1_BIT_3_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_2_BIT_3_1 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_2_BIT_3_2 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_2_BIT_3_3 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_2_BIT_3_4 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_4_BIT_3_1 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_4_BIT_3_2 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_4_BIT_3_3 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_4_BIT_3_4 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_8_BIT_3_1 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_8_BIT_3_2 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_8_BIT_3_3 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_8_BIT_3_4 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_16_BIT_3_1 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_16_BIT_3_2 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_16_BIT_3_3 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_16_BIT_3_4 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_1_BIT_4_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_1_BIT_4_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_1_BIT_4_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_1_BIT_4_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		SIGNAL_2_BIT_4_1 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_2_BIT_4_2 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_2_BIT_4_3 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_2_BIT_4_4 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		SIGNAL_4_BIT_4_1 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_4_BIT_4_2 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_4_BIT_4_3 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_4_BIT_4_4 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		SIGNAL_8_BIT_4_1 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_8_BIT_4_2 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_8_BIT_4_3 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_8_BIT_4_4 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		SIGNAL_16_BIT_4_1 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_16_BIT_4_2 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_16_BIT_4_3 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_16_BIT_4_4 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		TRIGGER_1_BIT_1 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_1_BIT_2 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_1_BIT_3 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_1_BIT_4 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_2_BIT_1 : IN std_logic_vector(1 downto 0);
		TRIGGER_2_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_2_BIT_2 : IN std_logic_vector(1 downto 0);
		TRIGGER_2_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_2_BIT_3 : IN std_logic_vector(1 downto 0);
		TRIGGER_2_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_2_BIT_4 : IN std_logic_vector(1 downto 0);
		TRIGGER_2_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_4_BIT_1 : IN std_logic_vector(3 downto 0);
		TRIGGER_4_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_4_BIT_2 : IN std_logic_vector(3 downto 0);
		TRIGGER_4_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_4_BIT_3 : IN std_logic_vector(3 downto 0);
		TRIGGER_4_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_4_BIT_4 : IN std_logic_vector(3 downto 0);
		TRIGGER_4_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_8_BIT_1 : IN std_logic_vector(7 downto 0);
		TRIGGER_8_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_8_BIT_2 : IN std_logic_vector(7 downto 0);
		TRIGGER_8_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_8_BIT_3 : IN std_logic_vector(7 downto 0);
		TRIGGER_8_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_8_BIT_4 : IN std_logic_vector(7 downto 0);
		TRIGGER_8_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_16_BIT_1 : IN std_logic_vector(15 downto 0);
		TRIGGER_16_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_16_BIT_2 : IN std_logic_vector(15 downto 0);
		TRIGGER_16_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_16_BIT_3 : IN std_logic_vector(15 downto 0);
		TRIGGER_16_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_16_BIT_4 : IN std_logic_vector(15 downto 0);
		TRIGGER_16_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_REARM_TOGGLE : IN std_logic;
		FORCE_TRIGGER_TOGGLE : IN std_logic;
		SREG250_READ_TOGGLE : IN std_logic;
		START_CAPTURE_TOGGLE : IN std_logic;          
		REG250 : OUT std_logic_vector(7 downto 0);
		REG251 : OUT std_logic_vector(7 downto 0);
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;



--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
-- Suffix _D indicates a one CLK delayed version of the net with the same name
-- Suffix _X indicates an extended precision version of the net with the same name
-- Suffix _N indicates an inverted version of the net with the same name

--// CLOCKS, RESETS
signal CLK_DDR2: std_logic;
signal CLK_P: std_logic;
signal CLK_IO: std_logic;
signal USB_CLK60G: std_logic;
signal PLL_LOCKED: std_logic;
signal ASYNC_RESET_PLL: std_logic;
signal ASYNC_RESET: std_logic;
signal RESET_STATE: integer range 0 to 3 := 0;
	-- asynchronous reset


signal CLK_IN_B: std_logic;
signal CLK_ING:	std_logic;
signal RESET_COUNTER: std_logic_vector(23 downto 0) := x"000000";	-- initialize for simulations
	-- spans 2^23/60MHz = 140ms
	
--// INPUT SIGNALS
signal DATA_I_IN: std_logic_vector(9 downto 0);
signal DATA_Q_IN: std_logic_vector(9 downto 0);
signal SAMPLE_CLK_IN: std_logic;
signal DATA_I_IN_A: std_logic_vector(9 downto 0);
signal DATA_Q_IN_A: std_logic_vector(9 downto 0);
signal DATA_I_IN_B: std_logic_vector(9 downto 0);
signal DATA_Q_IN_B: std_logic_vector(9 downto 0);
signal DATA1_I: std_logic_vector(9 downto 0);
signal DATA1_Q: std_logic_vector(9 downto 0);
signal A_BN: std_logic;
signal A_BN_DF: std_logic;
signal DATA1A_I: std_logic_vector(11 downto 0);
signal DATA1A_Q: std_logic_vector(11 downto 0);

--// USB Interface for M&C
signal USB_ULPI_STP_LOCAL: std_logic;
signal RX_USB: std_logic_vector(7 downto 0); 
signal RX_USB_SAMPLE_CLK: std_logic;
signal RX_USB_SAMPLE_CLK_REQ: std_logic;
signal RX_USB_BUFFER_EMPTY: std_logic;
signal RX_USB_BUFFER_EMPTY_D: std_logic;
signal RX_USB_BUFFER_EMPTY_D2: std_logic;
signal SREG254_READ_TOGGLE_D: std_logic;
signal SREG254_READ_TOGGLE_D2: std_logic;
signal TX_USB: std_logic_vector(7 downto 0); 
signal TX_USB_SAMPLE_CLK: std_logic;
signal TX_USB_TOGGLE: std_logic;
signal TX_USB_TOGGLE_D: std_logic;
signal TX_USB_TOGGLE_D2: std_logic;
signal PHY_VENDOR_ID: std_logic_vector(7 downto 0);
signal USB_TP: std_logic_vector(20 downto 1);
signal USB_CS1: std_logic_vector(7 downto 0);
signal USB_CS1_CLK: std_logic;
signal USB_CS2: std_logic_vector(7 downto 0);
signal USB_CS2_CLK: std_logic;
signal USB_CS3: std_logic_vector(7 downto 0);
signal USB_CS3_CLK: std_logic;
signal USB_T1: std_logic;
signal USB_T1_CLK: std_logic;
signal USB_T2: std_logic;
signal USB_T2_CLK: std_logic;

--// COM-5401 QUAD 10/100/1000 Mbps Ethernet PHYs -------
signal MAC_ADDR: std_logic_vector(47 downto 0);
signal MAC_RX_CONFIG: std_logic_vector(15 downto 0);

-- RGMII
signal LAN1_TXC: std_logic;  -- tx clock
signal LAN1_TXD: std_logic_vector(3 downto 0);  -- tx data
signal LAN1_TX_CTL: std_logic;  -- tx control: combines TX_EN and TX_ER
			-- valid at the falling clock edge
signal LAN1_RXC: std_logic;  -- receive clock
			-- must be delayed by 1.5 to 2.1 ns to prevent glitches
signal LAN1_RXD: std_logic_vector(3 downto 0);  -- receive data
signal LAN1_RX_CTL: std_logic;  -- receive control. combines RX_DV and RX_ER
			-- valid at the falling clock edge
			-- Note: Micrel KSZ9021RN PHY defines these as dual-function signals.
			-- Set the strapping options in the .ucf constraint file.
signal LAN1_RESET_N: std_logic;
			-- PHY reset
signal LAN1_MCLK: std_logic;

-- GMII
signal LAN1_GMII_CRS : std_logic := '0';
signal LAN1_GMII_COL : std_logic := '0';
signal LAN1_GMII_RX_CLK : std_logic := '0';
signal LAN1_GMII_RXD : std_logic_vector(7 downto 0);
signal LAN1_GMII_RX_DV : std_logic := '0';
signal LAN1_GMII_RX_ER : std_logic := '0';   
signal LAN1_MII_TX_CLK : std_logic := '0';
signal LAN1_GMII_TX_CLK : std_logic := '0';
signal LAN1_GMII_TXD : std_logic_vector(7 downto 0);
signal LAN1_GMII_TX_EN : std_logic := '0';
signal LAN1_GMII_TX_ER : std_logic := '0';


signal COM5401_TP: std_logic_vector(10 downto 1);
signal LAN1_PHY_ID: std_logic_vector(15 downto 0);
signal LAN1_RX_DATA: std_logic_vector(7 downto 0);
signal LAN1_RX_SAMPLE_CLK: std_logic;
signal LAN1_RX_SAMPLE_CLK_REQ: std_logic;
signal LAN1_MAC_TX_DATA: std_logic_vector(7 downto 0);
signal LAN1_MAC_TX_DATA_VALID: std_logic;
signal LAN1_MAC_TX_EOF: std_logic;
signal LAN1_MAC_TX_CTS: std_logic;

--// ComScope traces
signal CS_CLKG: std_logic;
signal S1_1: std_logic_vector(7 downto 0);	
signal S1_1_CLK: std_logic;
signal S1_1B_CLK: std_logic;
signal S1_2: std_logic_vector(7 downto 0);	
signal S1_2_CLK: std_logic;
signal S1_2B_CLK: std_logic;
signal S1_3: std_logic_vector(7 downto 0);	
signal S1_3_CLK: std_logic;
signal S1_3B_CLK: std_logic;
signal S1_4: std_logic_vector(7 downto 0);	
signal S1_4_CLK: std_logic;
signal S1_4B_CLK: std_logic;
signal S2_1: std_logic_vector(7 downto 0);	
signal S2_1_CLK: std_logic;
signal S2_1B_CLK: std_logic;
signal S2_2: std_logic_vector(7 downto 0);	
signal S2_2_CLK: std_logic;
signal S2_2B_CLK: std_logic;
signal S2_3: std_logic_vector(7 downto 0);	
signal S2_3_CLK: std_logic;
signal S2_3B_CLK: std_logic;
signal S2_4: std_logic_vector(7 downto 0);	
signal S2_4_CLK: std_logic;
signal S2_4B_CLK: std_logic;
signal S3_1: std_logic_vector(7 downto 0);	
signal S3_1_CLK: std_logic;
signal S3_1B_CLK: std_logic;
signal S3_2: std_logic_vector(7 downto 0);	
signal S3_2_CLK: std_logic;
signal S3_2B_CLK: std_logic;
signal S3_3: std_logic_vector(7 downto 0);	
signal S3_3_CLK: std_logic;
signal S3_3B_CLK: std_logic;
signal S3_4: std_logic_vector(7 downto 0);	
signal S3_4_CLK: std_logic;
signal S3_4B_CLK: std_logic;

signal T1: std_logic;
signal T1_CLK: std_logic;
signal T2: std_logic;
signal T2_CLK: std_logic;

--// TEST POINTS
signal TP1: std_logic_vector(10 downto 1);
signal TP2: std_logic_vector(10 downto 1);

signal TRIGGER_REARM_TOGGLE: std_logic:= '0';
signal FORCE_TRIGGER_TOGGLE: std_logic:= '0';
signal START_CAPTURE_TOGGLE: std_logic:= '0';
signal SREG250_READ_TOGGLE: std_logic;

--// ARM co-processor interface
signal UC_WEBG: std_logic;  -- WE# through global buffer
signal UC_ADDRESS: std_logic_vector(7 downto 0);
signal UC_AD_LOCAL: std_logic_vector(7 downto 0);
signal UC_RDN_D: std_logic;
signal UC_RDN_D2: std_logic;
signal CONFIG_CHANGE_TOGGLE: std_logic;
signal CONFIG_CHANGE_TOGGLE_D: std_logic;
signal CONFIG_CHANGE_TOGGLE_D2: std_logic;
signal CONFIG_CHANGE_PULSE: std_logic;

--// Control Registers
signal REG0: std_logic_vector(7 downto 0);
signal REG1: std_logic_vector(7 downto 0);
signal REG2: std_logic_vector(7 downto 0);
signal REG3: std_logic_vector(7 downto 0);
signal REG4: std_logic_vector(7 downto 0);
signal REG5: std_logic_vector(7 downto 0);
signal REG6: std_logic_vector(7 downto 0);
signal REG7: std_logic_vector(7 downto 0);
signal REG8: std_logic_vector(7 downto 0);
signal REG9: std_logic_vector(7 downto 0);
signal REG255: std_logic_vector(7 downto 0);

--// Status Registers
signal SREG0: std_logic_vector(7 downto 0);
signal SREG1: std_logic_vector(7 downto 0);
signal SREG2: std_logic_vector(7 downto 0);
signal SREG3: std_logic_vector(7 downto 0);
signal SREG4: std_logic_vector(7 downto 0);
signal SREG5: std_logic_vector(7 downto 0);
signal SREG6: std_logic_vector(7 downto 0);
signal SREG7: std_logic_vector(7 downto 0);
signal SREG8: std_logic_vector(7 downto 0);
signal SREG9: std_logic_vector(7 downto 0);
signal SREG254_READ_TOGGLE: std_logic;			

--// ComScope control registers
signal REG237: std_logic_vector(7 downto 0):= "00000000";
signal REG238: std_logic_vector(7 downto 0):= "00000000";
signal REG239: std_logic_vector(7 downto 0):= "00000000";
signal REG240: std_logic_vector(7 downto 0):= "00001101";	-- Trace 1 signal selection
signal REG241: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG242: std_logic_vector(7 downto 0):= "00001110";	-- Trace 2 signal selection
signal REG243: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG244: std_logic_vector(7 downto 0):= "00000000";	-- Trace 3 signal selection
signal REG245: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG246: std_logic_vector(7 downto 0):= "00000000";	-- Trace 4 signal selection
signal REG247: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG248: std_logic_vector(7 downto 0):= "10001101";	-- Trigger edge, trigger signal
signal REG249: std_logic_vector(7 downto 0):= "10111111";	-- Trigger threshold
signal REG250: std_logic_vector(7 downto 0):= "00000000";
signal REG251: std_logic_vector(7 downto 0):= "00000000";



signal VAR_CLK: std_logic; -- REG1(0) '1' = 40MHz '0' = 60 MHz
signal DIFFERENCE_OUT: std_logic_vector(30 downto 1);
signal ERROR_CNT: std_logic_vector(30 downto 1);
signal TEST_DATA_OUT: std_logic_vector(30 downto 1);
signal TEST_DATA_OUT_LOCAL: std_logic_vector(30 downto 1);
signal TEST_DATA_IN: std_logic_vector(30 downto 1);   
signal TEST_DATA_IN_D: std_logic_vector(30 downto 1);   

signal TTTP1: std_logic;
signal TTTP2: std_logic;


--// FPGA option and revision (ASCII format)
-- These two ASCII characters appear in the Comblock Control Center.
-- Very helpful in identifying which firmware version is currently running
-- in the FPGA. 
-- '0' = 48
-- 'A' = 65
constant OPTION: std_logic_vector(7 downto 0) := x"36";	-- '6'
constant REVISION: std_logic_vector(7 downto 0) := x"30";	-- '0'
constant PRODUCTION_TEST: std_logic  := '1';  -- configure the FPGA for production test (1) or not (0)
--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
begin
--// CLOCKS, RESET ---------------------
-- Generate miscellaneous global clocks and resets from the 
-- reference 60 MHz clock (from the USB PHY). 
-- FOR MOST APPLICATIONS, KEEP THIS SECTION UNCHANGED.
-- Most Common changes: change the various system clock frequencies within CLKGEN_PLL 

RESET_STATE_MACHINE_001: process(USB_CLK60G)
begin
	if rising_edge(USB_CLK60G) then
		if(RESET_STATE = 0) then
			-- hold PLL in reset for 2.2 ms after FPGA configuration
			-- while the USB PHY switches from 30 MHz clock to 60 MHz clock.
			if(RESET_COUNTER(17) = '0') then
				RESET_COUNTER <= RESET_COUNTER + 1;
			else
				-- move to the next state
				RESET_COUNTER <= (others => '0');
				RESET_STATE <= 1;
			end if;
		
		elsif(RESET_STATE = 1) then
			-- PLL need time to lock. The reset of the application is still in reset
			if(RESET_COUNTER(17) = '0') then
				-- wait a bit before asserting the PLL lock
				RESET_COUNTER <= RESET_COUNTER + 1;
			elsif(PLL_LOCKED = '1') then
				-- assert the PLL lock
				RESET_STATE <= 2;
			end if;
		end if;
		
	end if;
end process;

ASYNC_RESET_PLL <= '1' when (RESET_STATE = 0) else '0';	-- 2.2ms
ASYNC_RESET <= '0' when (RESET_STATE = 2) else '1';	-- 4.4ms


-- force selection of correct IBUF
--IBUF_003: IBUF port map(I => LEFT_CONNECTOR_A(1), O => CLK_IN_B);

-- Global buffers
--BUFG_004: BUFG  port map (I=> CLK_IN_B, O=> CLK_ING);	
	-- external input clock
BUFG_006: BUFG  port map (I=> UC_WEB_IN, O=> UC_WEBG);	
	-- ARM WE#


Inst_CLKGEN_PLL: CLKGEN_PLL PORT MAP(
	CLKREF_IN => USB_CLK60,
	CLKOUT0G => USB_CLK60G,		-- USB clock, global
	CLKOUT1G => CLK_P,			-- processing clock, global
	CLKOUT2G => CLK_DDR2,		-- DDR2 SDRAM clock, global
	LOCKED_PLL => PLL_LOCKED
);



--// USB INTERFACE ---------------------
-- The USB component is available in .ngc form (not source code).
-- Two virtual channels are available:
-- Channel 1 for Monitoring and Control. PART OF THE FRAMEWORK. DO NOT CHANGE.
-- Channel 2 is a payload channel (available for custom applications). 
-- Tie the channel 2 inputs and outputs to the application input and 
-- output streams as needed.
USB20ULPI_001: USB20ULPI port map(
	USB_CLK60G => USB_CLK60G,
	SYNC_RESET => ASYNC_RESET,
	CLK_P => CLK_P,

	-- interface with USB PHY. Direct connection to I/O pins.
	USB_ULPI_DATA => USB_ULPI_DATA,
	USB_ULPI_STP => USB_ULPI_STP_LOCAL,
	USB_ULPI_NXT => USB_ULPI_NXT,
	USB_ULPI_DIR => USB_ULPI_DIR,

	-- M&C channel. Interfaces with ARM uC. Uses data stream 1
	DATA1_OUT => RX_USB,
	DATA1_OUT_SAMPLE_CLK => RX_USB_SAMPLE_CLK,
	DATA1_OUT_BUFFER_EMPTY => RX_USB_BUFFER_EMPTY,
	DATA1_OUT_SAMPLE_CLK_REQ => RX_USB_SAMPLE_CLK_REQ,
	DATA1_IN => TX_USB,
   DATA1_IN_SAMPLE_CLK => TX_USB_SAMPLE_CLK,
	DATA1_IN_SAMPLE_CLK_REQ => open,	
		-- ARM uC is much slower than USB. no need to verify tx flow control.

	-- Payload channel. Data stream 2
	DATA2_OUT => open,
	DATA2_OUT_SAMPLE_CLK => open,
	DATA2_OUT_BUFFER_EMPTY => open,
	DATA2_OUT_SAMPLE_CLK_REQ => '0',
	DATA2_IN => LAN1_RX_DATA,
	DATA2_IN_SAMPLE_CLK => LAN1_RX_SAMPLE_CLK,
	DATA2_IN_SAMPLE_CLK_REQ => LAN1_RX_SAMPLE_CLK_REQ,
	
	PHY_VENDOR_ID => PHY_VENDOR_ID,
	CS1 => USB_CS1,
	CS1_CLK => USB_CS1_CLK,
	CS2 => USB_CS2,
	CS2_CLK => USB_CS2_CLK,
	CS3 => USB_CS3,
	CS3_CLK => USB_CS3_CLK,
	T1 => USB_T1,
	T1_CLK => USB_T1_CLK,
	T2 => USB_T2,
	T2_CLK => USB_T2_CLK,
	USB_TP => USB_TP
);
USB_ULPI_STP <= USB_ULPI_STP_LOCAL;

--// COM-5401 QUAD 10/100/1000 Mbps Ethernet PHYs -------
MAC_ADDR <= REG5 & REG4 & REG3 & REG2 & REG1 & REG0;
MAC_RX_CONFIG <= REG7 & REG6;

-- RGMII interface COM-1600. Hardware tested.
--LAN1_RXC <= LEFT_CONNECTOR_A(1);
--LAN1_RX_CTL <= LEFT_CONNECTOR_A(2);
--LAN1_RXD(3 downto 0) <= LEFT_CONNECTOR_A(6 downto 3);
--LEFT_CONNECTOR_A(6 downto 1) <=  (others => 'Z');	-- Input-only: make sure that out is tri-stated.
--LEFT_CONNECTOR_A(7) <= LAN1_TXC;
--LEFT_CONNECTOR_A(8) <= LAN1_TX_CTL;
--LEFT_CONNECTOR_A(12 downto 9) <= LAN1_TXD(3 downto 0); 
--LEFT_CONNECTOR_A(14 downto 13) <= (others => 'Z');	-- Input-only: make sure that out is tri-stated.
--LEFT_CONNECTOR_A(15) <= LAN1_RESET_N;
--LEFT_CONNECTOR_A(16) <= LAN1_MCLK;

-- GMII interface. no hardware to test it with at this time.
LAN1_GMII_RX_CLK <= LEFT_CONNECTOR_A(1);
LAN1_GMII_RX_DV <= LEFT_CONNECTOR_A(2);
LAN1_GMII_RX_ER <= LEFT_CONNECTOR_A(3);
LAN1_GMII_RXD <= LEFT_CONNECTOR_A(11 downto 4);
LAN1_GMII_CRS <= LEFT_CONNECTOR_A(12);
LAN1_GMII_COL <= LEFT_CONNECTOR_A(13);
LAN1_MII_TX_CLK <= LEFT_CONNECTOR_A(14);
LEFT_CONNECTOR_A(14 downto 1) <=  (others => 'Z');	-- Input-only: make sure that out is tri-stated.
LEFT_CONNECTOR_A(15) <= LAN1_GMII_TX_CLK;
LEFT_CONNECTOR_A(16) <= LAN1_GMII_TX_EN;
LEFT_CONNECTOR_A(18) <= LAN1_MCLK;
LEFT_CONNECTOR_A(19) <= LAN1_GMII_TX_ER;
LEFT_CONNECTOR_A(27 downto 20) <= LAN1_GMII_TXD; 

-- Temporary test points
LEFT_CONNECTOR_A(38 downto 29) <= COM5401_TP;

LAN_001: COM5401 
GENERIC MAP(
	MII_SEL => '1',   	-- select which MII interface: 0 = RGMII, 1 = GMII/MII
	PHY_ADDR => "00100",	-- PHY_AD0/1 pulled-down by 1KOhm, PHY_AD2 pulled-up in .ucf file.
	CLK_FREQUENCY => 120
)
PORT MAP(
	CLK => CLK_P,
	ASYNC_RESET => ASYNC_RESET,
	MAC_TX_CONFIG => X"0003",	-- MAC must must provide pad + crc32
	MAC_RX_CONFIG => MAC_RX_CONFIG,	-- promiscuous mode, crc32, accept broadcast/multicast
	MAC_ADDR => MAC_ADDR,
	PHY_CONFIG_CHANGE => '0',	
	PHY_RESET => '0',
	SPEED => "11",	-- unused here. Use defaults within.
	DUPLEX => '1',	-- unused here. Use defaults within.
	TEST_MODE => "00",	-- unused here. Use defaults within.
	POWER_DOWN => '0', -- unused here. Use defaults within.
	CLK_SKEW => x"0000",
	MAC_TX_DATA => LAN1_MAC_TX_DATA,
	MAC_TX_DATA_VALID => LAN1_MAC_TX_DATA_VALID,
	MAC_TX_EOF => LAN1_MAC_TX_EOF,
	MAC_TX_CTS => LAN1_MAC_TX_CTS,
	MAC_RX_DATA => LAN1_RX_DATA,	
	MAC_RX_DATA_VALID => LAN1_RX_SAMPLE_CLK,
	MAC_RX_SOF => open,
	MAC_RX_EOF => open,
	MAC_RX_CTS => LAN1_RX_SAMPLE_CLK_REQ,
	TXC => open,	-- RGMII interface (unused here) ----------------
	TXD => open,
	TX_CTL => open,
	RXC => '0',
	RXD => x"0",
	RX_CTL => '0',
	RESET_N => LAN1_RESET_N,  -- end of RGMII interface ----------
	MCLK => LAN1_MCLK,				-- PHY management data clock
	MDIO => LEFT_CONNECTOR_A(17),	-- PHT management data I/O
	MII_TX_CLK => LAN1_MII_TX_CLK,	-- MII/GMII interface  -----------------
	GMII_TX_CLK => LAN1_GMII_TX_CLK,
	GMII_MII_TXD => LAN1_GMII_TXD,
	GMII_MII_TX_EN => LAN1_GMII_TX_EN,
	GMII_MII_TX_ER => LAN1_GMII_TX_ER,
	GMII_MII_CRS => LAN1_GMII_CRS,
	GMII_MII_COL => LAN1_GMII_COL,
	GMII_MII_RX_CLK => LAN1_GMII_RX_CLK,
	GMII_MII_RXD => LAN1_GMII_RXD,
	GMII_MII_RX_DV => LAN1_GMII_RX_DV,
	GMII_MII_RX_ER => LAN1_GMII_RX_ER,  -- end of MII/GMII interface ------
	LINK_STATUS => open,
	SPEED_STATUS => open,
	DUPLEX_STATUS => open,
	PHY_ID => LAN1_PHY_ID,
	CS_CLKG => CS_CLKG,
	CS1 => S1_1,
	CS1_CLK => S1_1_CLK,
	CS2 => S2_1,
	CS2_CLK => S2_1_CLK,
	TP => COM5401_TP
);

SREG8 <= LAN1_PHY_ID(7 downto 0);
SREG9 <= LAN1_PHY_ID(15 downto 8);

-- send periodic packets to LAN
Inst_LAN_TX_TEST: LAN_TX_TEST PORT MAP(
	CLK => CLK_P,
	ASYNC_RESET => ASYNC_RESET,
	MAC_TX_DATA => LAN1_MAC_TX_DATA,
	MAC_TX_DATA_VALID => LAN1_MAC_TX_DATA_VALID,
	MAC_TX_EOF => LAN1_MAC_TX_EOF,
	MAC_TX_CTS => LAN1_MAC_TX_CTS
);

--//====================================================
-- START OF MAIN APPLICATION CODE
--//====================================================
--
-- 1. Modify CLKGEN_PLL to generate the desired clock frequencies
-- 
-- 2. Define Left connector signals. _A for top row, _B for bottom row. For example:
-- LEFT_CONNECTOR_A(10 downto 1) <= USB_TP(20 downto 11);
--
-- 3. Define Right connector signals. _A for top row, _B for bottom row. For example:
-- RIGHT_CONNECTOR_A(38) <= COM3504_AUX_SPI5;
-- RIGHT_CONNECTOR_B(38) <= COM3504_AUX_SPI5;
-- 
-- 4. Connect the control registers to your application's controls. For example:
-- your 32-bit control signal <= REG0 & REG1 & REG2 & REG3

-- 5. Connect the your monitoring signals to the status registers. For example:
--SREG0 <= DIFFERENCE_OUT(8 downto 1);
--SREG1 <= DIFFERENCE_OUT(16 downto 9);
--SREG2 <= DIFFERENCE_OUT(24 downto 17);
-- 
-- 6. Connect your monitoring signals to ComScope traces so as to visualize internal FPGA signals
--
-- 7. Write your application code
--
-- 8. Assign OPTION and REVISION constants (ASCII characters) to your code to detect which 
-- code is running on the FPGA.
--
----//====================================================
---- END OF MAIN APPLICATION CODE
----//====================================================
--		
--// COMSCOPE -----------------------------------------------------
--  Comment in/out as needed 
-- 
-- Define Comscope traces here 
-- Trace 1
--S1_1 <= COM3504_ADC1_DOUT(11 downto 4);
--S1_1_CLK <= '1';

-- Trace 2
--S2_1 <= COM3504_ADC2_DOUT(11 downto 4);
--S2_1_CLK <= '1';

-- Trace 3
--S3_1 <= COM3504_AUXADC1_DOUT(11 downto 4);
--S3_1_CLK <= '1';

-- Trigger (1-bit format, undefine
--T1 <= USB_T1;
--T1_CLK <= USB_T1_CLK;
--T2 <= USB_T2;
--T2_CLK <= USB_T2_CLK;

S1_1B_CLK <= S1_1_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
S1_2B_CLK <= S1_2_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
S1_3B_CLK <= S1_3_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
S1_4B_CLK <= S1_4_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock

S2_1B_CLK <= S2_1_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
S2_2B_CLK <= S2_2_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
S2_3B_CLK <= S2_3_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
S2_4B_CLK <= S2_4_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock

S3_1B_CLK <= S3_1_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
S3_2B_CLK <= S3_2_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
S3_3B_CLK <= S3_3_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
S3_4B_CLK <= S3_4_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock


COMSCOPE_001: COMSCOPE 
generic map(
	TRACE1_ENABLED => '1',
	TRACE2_ENABLED => '1',
	TRACE3_ENABLED => '0',
	TRACE4_ENABLED => '0'
)
port map(
   CLK => CS_CLKG,
	ASYNC_RESET => ASYNC_RESET,
	SIGNED_REPRESENTATION_U_SIGNED_N => REG248(6),	-- trigger format signed(1) or unsigned(0)
	REG237 => REG237,
	REG238 => REG238,
	REG239 => REG239,
	REG240 => REG240,
	REG241 => REG241,
	REG242 => REG242,
	REG243 => REG243,
	REG244 => REG244,
	REG245 => REG245,
	REG246 => REG246,
	REG247 => REG247,
	REG248 => REG248,
	REG249 => REG249,
	SIGNAL_1_BIT_1_1 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_1_1 => '0',
	SIGNAL_1_BIT_1_2 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_1_2 => '0',
	SIGNAL_1_BIT_1_3 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_1_3 => '0',
	SIGNAL_1_BIT_1_4 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_1_4 => '0',
	SIGNAL_2_BIT_1_1 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_1_1 => '0',
	SIGNAL_2_BIT_1_2 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_1_2 => '0',
	SIGNAL_2_BIT_1_3 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_1_3 => '0',
	SIGNAL_2_BIT_1_4 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_1_4 => '0',
	SIGNAL_4_BIT_1_1 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_1_1 => '0',
	SIGNAL_4_BIT_1_2 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_1_2 => '0',
	SIGNAL_4_BIT_1_3 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_1_3 => '0',
	SIGNAL_4_BIT_1_4 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_1_4 => '0',
	SIGNAL_8_BIT_1_1 => S1_1,
	SIGNAL_8_BIT_SAMPLE_CLK_1_1 => S1_1B_CLK,
	SIGNAL_8_BIT_1_2 => S1_2,
	SIGNAL_8_BIT_SAMPLE_CLK_1_2 => S1_2B_CLK,
	SIGNAL_8_BIT_1_3 => S1_3,
	SIGNAL_8_BIT_SAMPLE_CLK_1_3 => S1_3B_CLK,
	SIGNAL_8_BIT_1_4 => S1_4,
	SIGNAL_8_BIT_SAMPLE_CLK_1_4 => S1_4B_CLK,
	SIGNAL_16_BIT_1_1 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_1_1 => '0',
	SIGNAL_16_BIT_1_2 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_1_2 => '0',
	SIGNAL_16_BIT_1_3 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_1_3 => '0',
	SIGNAL_16_BIT_1_4 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_1_4 => '0',
	SIGNAL_1_BIT_2_1 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_2_1 => '0',
	SIGNAL_1_BIT_2_2 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_2_2 => '0',
	SIGNAL_1_BIT_2_3 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_2_3 => '0',
	SIGNAL_1_BIT_2_4 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_2_4 => '0',
	SIGNAL_2_BIT_2_1 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_2_1 => '0',
	SIGNAL_2_BIT_2_2 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_2_2 => '0',
	SIGNAL_2_BIT_2_3 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_2_3 => '0',
	SIGNAL_2_BIT_2_4 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_2_4 => '0',
	SIGNAL_4_BIT_2_1 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_2_1 => '0',
	SIGNAL_4_BIT_2_2 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_2_2 => '0',
	SIGNAL_4_BIT_2_3 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_2_3 => '0',
	SIGNAL_4_BIT_2_4 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_2_4 => '0',
	SIGNAL_8_BIT_2_1 => S2_1,
	SIGNAL_8_BIT_SAMPLE_CLK_2_1 => S2_1B_CLK,
	SIGNAL_8_BIT_2_2 => S2_2,
	SIGNAL_8_BIT_SAMPLE_CLK_2_2 => S2_2B_CLK,
	SIGNAL_8_BIT_2_3 => S2_3,
	SIGNAL_8_BIT_SAMPLE_CLK_2_3 => S2_3B_CLK,
	SIGNAL_8_BIT_2_4 => S2_4,
	SIGNAL_8_BIT_SAMPLE_CLK_2_4 => S2_4B_CLK,
	SIGNAL_16_BIT_2_1 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_2_1 => '0',
	SIGNAL_16_BIT_2_2 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_2_2 => '0',
	SIGNAL_16_BIT_2_3 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_2_3 => '0',
	SIGNAL_16_BIT_2_4 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_2_4 => '0',
	SIGNAL_1_BIT_3_1 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_3_1 => '0',
	SIGNAL_1_BIT_3_2 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_1_BIT_3_3 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_1_BIT_3_4 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_2_BIT_3_1 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_3_1 => '0',
	SIGNAL_2_BIT_3_2 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_2_BIT_3_3 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_2_BIT_3_4 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_4_BIT_3_1 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_3_1 => '0',
	SIGNAL_4_BIT_3_2 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_4_BIT_3_3 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_4_BIT_3_4 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_8_BIT_3_1 => S3_1,
	SIGNAL_8_BIT_SAMPLE_CLK_3_1 => S3_1B_CLK,
	SIGNAL_8_BIT_3_2 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_8_BIT_3_3 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_8_BIT_3_4 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_16_BIT_3_1 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_3_1 => '0',
	SIGNAL_16_BIT_3_2 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_16_BIT_3_3 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_16_BIT_3_4 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_1_BIT_4_1 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_1_BIT_4_2 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_1_BIT_4_3 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_1_BIT_4_4 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_4_4 => '0',
	SIGNAL_2_BIT_4_1 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_2_BIT_4_2 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_2_BIT_4_3 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_2_BIT_4_4 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_4_4 => '0',
	SIGNAL_4_BIT_4_1 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_4_BIT_4_2 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_4_BIT_4_3 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_4_BIT_4_4 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_4_4 => '0',
	SIGNAL_8_BIT_4_1 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_8_BIT_4_2 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_8_BIT_4_3 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_8_BIT_4_4 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_4_4 => '0',
	SIGNAL_16_BIT_4_1 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_16_BIT_4_2 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_16_BIT_4_3 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_16_BIT_4_4 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_4_4 => '0',
	TRIGGER_1_BIT_1 => T1,
	TRIGGER_1_BIT_SAMPLE_CLK_1 => T1_CLK,
	TRIGGER_1_BIT_2 => T2,
	TRIGGER_1_BIT_SAMPLE_CLK_2 => T2_CLK,
	TRIGGER_1_BIT_3 => '0',
	TRIGGER_1_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_1_BIT_4 => '0',
	TRIGGER_1_BIT_SAMPLE_CLK_4 => '0',
	TRIGGER_2_BIT_1 => (others => '0'),
	TRIGGER_2_BIT_SAMPLE_CLK_1 => '0',
	TRIGGER_2_BIT_2 => (others => '0'),
	TRIGGER_2_BIT_SAMPLE_CLK_2 => '0',
	TRIGGER_2_BIT_3 => (others => '0'),
	TRIGGER_2_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_2_BIT_4 => (others => '0'),
	TRIGGER_2_BIT_SAMPLE_CLK_4 => '0',
	TRIGGER_4_BIT_1 => (others => '0'),
	TRIGGER_4_BIT_SAMPLE_CLK_1 => '0',
	TRIGGER_4_BIT_2 => (others => '0'),
	TRIGGER_4_BIT_SAMPLE_CLK_2 => '0',
	TRIGGER_4_BIT_3 => (others => '0'),
	TRIGGER_4_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_4_BIT_4 => (others => '0'),
	TRIGGER_4_BIT_SAMPLE_CLK_4 => '0',
	TRIGGER_8_BIT_1 => (others => '0'),
	TRIGGER_8_BIT_SAMPLE_CLK_1 => '0',
	TRIGGER_8_BIT_2 => (others => '0'),
	TRIGGER_8_BIT_SAMPLE_CLK_2 => '0',
	TRIGGER_8_BIT_3 => (others => '0'),
	TRIGGER_8_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_8_BIT_4 => (others => '0'),
	TRIGGER_8_BIT_SAMPLE_CLK_4 => '0',
	TRIGGER_16_BIT_1 => (others => '0'),
	TRIGGER_16_BIT_SAMPLE_CLK_1 => '0',
	TRIGGER_16_BIT_2 => (others => '0'),
	TRIGGER_16_BIT_SAMPLE_CLK_2 => '0',
	TRIGGER_16_BIT_3 => (others => '0'),
	TRIGGER_16_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_16_BIT_4 => (others => '0'),
	TRIGGER_16_BIT_SAMPLE_CLK_4 => '0',
	REG250 => REG250,
	REG251 => REG251,
	TRIGGER_REARM_TOGGLE => TRIGGER_REARM_TOGGLE,
	FORCE_TRIGGER_TOGGLE => FORCE_TRIGGER_TOGGLE,
	SREG250_READ_TOGGLE => SREG250_READ_TOGGLE,
	START_CAPTURE_TOGGLE => START_CAPTURE_TOGGLE,
	TP => open
);



--// ARM CO-PROCESSOR INTERFACE ---------------------------------------------------
-- Primarily used for monitoring and control.
-- 8-bit shared address/data bus. clock synchronous.
-- PART OF THE FRAMEWORK. DO NOT CHANGE unless you want to 
-- add more control registers (see UC_WRITE_001) or status registers (see UC_READ_001).
-- 
-- Address latch
UC_ADDR_001: process(UC_CSIB_IN, UC_WEBG, UC_ALE_IN, UC_AD)
begin
	if rising_edge(UC_WEBG) then
		if (UC_CSIB_IN = '0') and (UC_ALE_IN = '1') then
			UC_ADDRESS <= UC_AD;
	  	end if;
  	end if;
end process;

-- Read status registers 
-- This template defines 10 status registers. 
-- User can define additional control registers using the same pattern. 
UC_READ_001: process(UC_ADDRESS, REG255, RX_USB, REG251, REG250, PHY_VENDOR_ID,
	SREG0, SREG1, SREG2, SREG3, SREG4, SREG5, SREG6, SREG7, SREG8, SREG9)
begin
	case(UC_ADDRESS) is
		-- ComBlock-reserved addresses ----
		when "11111111" => UC_AD_LOCAL <= REG255;		-- reg 255. Async serial from 3 connectors
		when "11111110" => UC_AD_LOCAL <= RX_USB;		-- reg 254 = 8-bit data from USB M&C channel
		when "11111101" => UC_AD_LOCAL <= REVISION;	-- reg 253 = fpga revision
		when "11111100" => UC_AD_LOCAL <= OPTION;		-- reg 252 = fpga option
		when "11111011" => UC_AD_LOCAL <= REG251;		-- reg 251 =comscope  status
		when "11111010" => UC_AD_LOCAL <= REG250;		-- reg 250 = comscope data byte
		
		-- User-defined status registers -------
		when "00000000" => UC_AD_LOCAL <= SREG0;
		when "00000001" => UC_AD_LOCAL <= SREG1;
		when "00000010" => UC_AD_LOCAL <= SREG2;
		when "00000011" => UC_AD_LOCAL <= SREG3;
		when "00000100" => UC_AD_LOCAL <= SREG4;
		when "00000101" => UC_AD_LOCAL <= SREG5;
		when "00000110" => UC_AD_LOCAL <= SREG6;
		when "00000111" => UC_AD_LOCAL <= PHY_VENDOR_ID;
-- TEST TEST TEST		when "00000111" => UC_AD_LOCAL <= SREG7;
		when "00001000" => UC_AD_LOCAL <= SREG8;
		when "00001001" => UC_AD_LOCAL <= SREG9;
		
		
		-- user can add more status registers as needed (200+)
		when others => UC_AD_LOCAL <= (others => '0');
	end case;
end process;

UC_AD <= UC_AD_LOCAL when (UC_CSIB_IN = '0') and (UC_REB_IN = '0') else (others => 'Z');
	-- when to drive the data bus between ARM and FPGA
	
-- toggle a few flags upon reading specific status registers
UC_READ_002: process(ASYNC_RESET, UC_REB_IN, UC_CSIB_IN, UC_ADDRESS, 
						SREG250_READ_TOGGLE, SREG254_READ_TOGGLE)
begin
	if(ASYNC_RESET = '1') then
		SREG250_READ_TOGGLE <= '0';
		SREG254_READ_TOGGLE <= '0';
	elsif rising_edge(UC_REB_IN) then
		if (UC_CSIB_IN = '0')  then
			if (UC_ADDRESS = 250) then
				SREG250_READ_TOGGLE <= not SREG250_READ_TOGGLE;
			end if;
			if (UC_ADDRESS = 254) then
				SREG254_READ_TOGGLE <= not SREG254_READ_TOGGLE;
			end if;
		end if;
	end if;
end process;
			
	
-- write to FPGA control registers
-- This template defines 10 control registers. 
-- User can define additional control registers using the same pattern. 
UC_WRITE_001: process(UC_CSIB_IN, UC_WEBG, UC_ALE_IN, UC_REB_IN, UC_AD)
begin
	if rising_edge(UC_WEBG) then
		if (UC_CSIB_IN = '0') and (UC_ALE_IN = '0') and (UC_REB_IN = '1')  then
			if (UC_ADDRESS = 0) then
				REG0 <= UC_AD;
			end if;
			if (UC_ADDRESS = 1) then
				REG1 <= UC_AD;
			end if;
			if (UC_ADDRESS = 2) then
				REG2 <= UC_AD;
			end if;
			if (UC_ADDRESS = 3) then
				REG3 <= UC_AD;
			end if;
			if (UC_ADDRESS = 4) then
				REG4 <= UC_AD;
			end if;
			if (UC_ADDRESS = 5) then
				REG5 <= UC_AD;
			end if;
			if (UC_ADDRESS = 6) then
				REG6 <= UC_AD;
			end if;
			if (UC_ADDRESS = 7) then
				REG7 <= UC_AD;
			end if;
			if (UC_ADDRESS = 8) then
				REG8 <= UC_AD;
			end if;
			if (UC_ADDRESS = 9) then
				REG9 <= UC_AD;
				CONFIG_CHANGE_TOGGLE <= not CONFIG_CHANGE_TOGGLE;	
				-- Configuration change toggles upon writing the last control register
				-- This happens invisibly to the user (only the ARM uC writes to REG9
				-- which is invible to the user and to the ComBlock Control Center).
			end if;
			-- user can add more control registers as needed (200+)



			-- Reserved:
			-- REG254 reserved for output serial
			if (UC_ADDRESS = 255) then
				-- REG255 write reserved for output serial (8-bit parallel format)
				-- route response to host query over USB
				TX_USB <= UC_AD;
				TX_USB_TOGGLE <= not TX_USB_TOGGLE;
			end if;
		end if;
	end if;
end process;

--// reserved COMSCOPE -------------------------------------------------------
-- Comment out if ComScope feature is unused
UC_WRITE_002: process(UC_CSIB_IN, UC_WEBG, UC_ADDRESS, UC_AD, 
	FORCE_TRIGGER_TOGGLE, TRIGGER_REARM_TOGGLE, START_CAPTURE_TOGGLE)
begin
	if rising_edge(UC_WEBG) then
		if (UC_CSIB_IN = '0') and (UC_ALE_IN = '0') and (UC_REB_IN = '1')  then
			-- Reserved for ComScope			
			if (UC_ADDRESS = 237) then
				REG237 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 238) then
				REG238 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 239) then
				REG239 <= UC_AD;
			end if;
			if (UC_ADDRESS = 240) then
				REG240 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 241) then
				REG241 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 242) then
				REG242 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 243) then
				REG243 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 244) then
				REG244 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 245) then
				REG245 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 246) then
				REG246 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 247) then
				REG247 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 248) then
				REG248 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 249) then
				REG249 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 250) then 
				-- detect one-shot force trigger	
				if(UC_AD(0) = '1') then	
					FORCE_TRIGGER_TOGGLE <= not(FORCE_TRIGGER_TOGGLE);
				end if;	
				-- detect one-shot re-arm	
				if(UC_AD(1) = '1') then	
					TRIGGER_REARM_TOGGLE <= not(TRIGGER_REARM_TOGGLE);
				end if;	
				-- start capturing again
				if(UC_AD(2) = '1') then	
					START_CAPTURE_TOGGLE <= not (START_CAPTURE_TOGGLE);
				end if;	
			end if;
		end if;
	end if;
end process;

--// end of COMSCOPE section -------------------------------------------------------

-- Reclock CONFIG_CHANGE_TOGGLE to be synchronous with processing clock CLK_P
RECLOCK_002: process(CLK_P)
begin
	if rising_edge(CLK_P) then
		CONFIG_CHANGE_TOGGLE_D <= CONFIG_CHANGE_TOGGLE;
		CONFIG_CHANGE_TOGGLE_D2 <= CONFIG_CHANGE_TOGGLE_D;
		if(CONFIG_CHANGE_TOGGLE_D /= CONFIG_CHANGE_TOGGLE_D2) then
			CONFIG_CHANGE_PULSE <= '1';
		else
			CONFIG_CHANGE_PULSE <= '0';
		end if;
	end if;
end process;


-- M&C USB interface --------------------------
-- REG255 reserved for reading serial port inputs
-- These signals are pulled high (to mimic stop bit).
REG255 <= "1111" & RX_USB_BUFFER_EMPTY & "111";
	-- When low, uC must read byte from USB


-- Reclock TX_USB_TOGGLE
RECLOCK_TX_USB_TOGGLE: process(CLK_P,TX_USB_TOGGLE)
begin
	if rising_edge(CLK_P) then
		TX_USB_TOGGLE_D <= TX_USB_TOGGLE;
		TX_USB_TOGGLE_D2 <= TX_USB_TOGGLE_D;
		if(TX_USB_TOGGLE_D /= TX_USB_TOGGLE_D2) then
			TX_USB_SAMPLE_CLK <= '1';
		else
			TX_USB_SAMPLE_CLK <= '0';
		end if;
	end if;
end process;

-- Immediately upon completing reading a byte from the USB, ask for the 
-- next one. 
-- RACE CONDITION??????? ARM IS FAST!!!!
RECLOCK_RDN_D: process(CLK_P, SREG254_READ_TOGGLE)
begin
	if rising_edge(CLK_P) then
		SREG254_READ_TOGGLE_D <= SREG254_READ_TOGGLE;
		SREG254_READ_TOGGLE_D2 <= SREG254_READ_TOGGLE_D;

		RX_USB_BUFFER_EMPTY_D <= RX_USB_BUFFER_EMPTY;
		RX_USB_BUFFER_EMPTY_D2 <= RX_USB_BUFFER_EMPTY_D;

		if (SREG254_READ_TOGGLE_D2 /= SREG254_READ_TOGGLE_D) then
			-- end of M&C byte read from ARM uC.
			if(RX_USB_BUFFER_EMPTY_D2 = '0') then
				-- last M&C byte read was over USB. Increment USB elastic buffer read pointer
				RX_USB_SAMPLE_CLK_REQ <= '1';
			end if;
		else
			RX_USB_SAMPLE_CLK_REQ <= '0';
		end if;
	end if;
end process;

end Behavioral;
