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-- Company: 
-- Engineer:
--
-- Create Date:   10:25:01 03/09/2010
-- Design Name:   
-- Module Name:   C:/Users/Admin/Documents/VHDL source/com-5401/sim/tbRESET_TIMER.vhd
-- Project Name:  com-5401
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RESET_TIMER
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tbRESET_TIMER IS
END tbRESET_TIMER;
 
ARCHITECTURE behavior OF tbRESET_TIMER IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
	COMPONENT RESET_TIMER
	generic (
		CLK_FREQUENCY: integer := 120
			-- CLK frequency in MHz. Needed to compute actual delays.
	);
	PORT(
		CLK : IN std_logic;
		RESET_START : IN std_logic;          
		RESET_COMPLETE : OUT std_logic;
		INITIAL_CONFIG_PULSE : OUT std_logic;
		RESET_N : OUT std_logic
		);
	END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal RESET_START : std_logic := '0';

 	--Outputs
   signal RESET_COMPLETE : std_logic;
   signal INITIAL_CONFIG_PULSE : std_logic;
   signal RESET_N : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 8.333 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: RESET_TIMER 
		GENERIC MAP(
			CLK_FREQUENCY => 120
		)
		PORT MAP (
          CLK => CLK,
          RESET_START => RESET_START,
          RESET_COMPLETE => RESET_COMPLETE,
          INITIAL_CONFIG_PULSE => INITIAL_CONFIG_PULSE,
          RESET_N => RESET_N
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
	RESET_START <= '0';
--process
--begin
--	RESET_START <= '0';
--	wait for 1ms;
--	RESET_START <= '1';
--	wait for 10 ns;
--	RESET_START <= '0';
--	wait;
--end process;

END;
