-------------------------------------------------------------
-- MSS copyright 2010-2012
--	Filename:  tbPHY_CONFIG.vhd
-- Author: Alain Zarembowitch / MSS
--	Version: 1
--	Date last modified: 3/5/10
-- Inheritance: 	N/A
-- See also: tbMII_MI for more detailed read/write timing.
-- 
-- description:  testbench configures the PHY and read a status register from the PHY over MDIO.
-- Objective is to check all PHY configuration transactions. 
-- Note: return status is undefined since the PHY's response is not simulated here.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tbPHY_CONFIG IS
END tbPHY_CONFIG;
 
ARCHITECTURE behavior OF tbPHY_CONFIG IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
	COMPONENT PHY_CONFIG
	GENERIC (
		PHY_ADDR: std_logic_vector(4 downto 0)
	);	
	PORT(
		SYNC_RESET : IN std_logic;
		CLK : IN std_logic;
		CONFIG_CHANGE : IN std_logic;
		PHY_RESET : IN std_logic;
		SPEED : IN std_logic_vector(1 downto 0);
		DUPLEX : IN std_logic;
		TEST_MODE : IN std_logic_vector(1 downto 0);
		POWER_DOWN : IN std_logic;
		CLK_SKEW: in std_logic_vector(9 downto 0);
		SREG_READ_START : IN std_logic;
		SREG_REGAD : IN std_logic_vector(8 downto 0);    
		MDIO : INOUT std_logic;      
		SREG_DATA : OUT std_logic_vector(15 downto 0);
		SREG_SAMPLE_CLK : OUT std_logic;
		MCLK : OUT std_logic;
		LINK_STATUS: out std_logic;  
		TP: out std_logic_vector(10 downto 1)
		);
	END COMPONENT;

   

   --Inputs
   signal SYNC_RESET : std_logic := '0';
   signal CLK : std_logic := '0';
   signal CONFIG_CHANGE : std_logic := '0';
   signal PHY_RESET : std_logic := '0';
   signal SPEED : std_logic_vector(1 downto 0) := (others => '0');
   signal DUPLEX : std_logic := '0';
   signal TEST_MODE : std_logic_vector(1 downto 0) := (others => '0');
   signal POWER_DOWN : std_logic := '0';
   signal SREG_READ_START : std_logic := '0';
   signal SREG_REGAD : std_logic_vector(4 downto 0) := (others => '0');

	--BiDirs
   signal MDIO : std_logic;

 	--Outputs
   signal SREG_DATA : std_logic_vector(15 downto 0);
   signal SREG_SAMPLE_CLK : std_logic;
   signal MCLK : std_logic;
	signal LINK_STATUS: std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
-- PHY monitoring and control
Inst_PHY_CONFIG: PHY_CONFIG 
GENERIC MAP(
	PHY_ADDR => "00100"
)
PORT MAP(
	SYNC_RESET => SYNC_RESET,  
	CLK => CLK,
	CONFIG_CHANGE => CONFIG_CHANGE,
	PHY_RESET => PHY_RESET,
	SPEED => SPEED,
	DUPLEX => DUPLEX,
	TEST_MODE => TEST_MODE,
	POWER_DOWN => POWER_DOWN,
	CLK_SKEW => "1111111111",
	SREG_READ_START => SREG_READ_START,
	SREG_REGAD => "000000010",	-- register 2: PHY Identifier 1
--	SREG_REGAD => "000000001",	-- register 1: Status word (link status, etc) 
--	SREG_REGAD => "100000001",	-- register 257: Strap status (extended register)
--	SREG_REGAD => "100000000",	-- register 256: common control (extended register)
	SREG_DATA => SREG_DATA,
	SREG_SAMPLE_CLK => SREG_SAMPLE_CLK,
	LINK_STATUS => LINK_STATUS,	-- generic method: read basic status register 1 (works for all PHYs)
	MCLK => MCLK,
	MDIO => MDIO,
	TP => open
);

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
 SYNC_RESET <= '0';
 PHY_RESET <= '1';
 SPEED <= "11";
 DUPLEX <= '1';
 TEST_MODE <= "00";
 POWER_DOWN <= '0';
 
 SREG_READ_START <= '0';
 SREG_REGAD <= "00000";
 

   -- Stimulus process
   stim_proc: process
   begin		
	CONFIG_CHANGE <= '0';
	wait for 1000 ns;
	CONFIG_CHANGE <= '1';
	wait for 10 ns;
	CONFIG_CHANGE <= '0';
   wait;
   end process;

END;
