-------------------------------------------------------------
--	Filename:  CLKGEN_PLL.VHD
-- Authors: 
--		Alain Zarembowitch / MSS, 
--	Version: 1
--	Date last modified: 8-18-10
-- Inheritance: 	none
--
-- description: Generate the key clocks (using a PLL) 
-- Generate the following clocks from the USB PHY 60 MHz frequency reference: 
-- CLKOUT0G: 60 MHz (primarily for USB SIE)
-- CLKOUT1G: 130 MHz processing clock CLK_P
-- CLK_DDR2G: 130 MHz DDR2 clock 
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;

entity CLKGEN_PLL is
port
 (-- Clock in ports (directly from input pin)
  CLKREF_IN           : in     std_logic;
  -- Clock out ports (after BUFGs)
  CLKOUT0G          : out    std_logic;
  CLKOUT1G          : out    std_logic;
  CLKOUT2G          : out    std_logic;
  -- Status and control signals
  LOCKED_PLL            : out    std_logic
 );
end entity;

architecture Behavioral of CLKGEN_PLL is
--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
signal CLKREF_INB: std_logic;
signal CLKOUT0: std_logic;
signal CLKOUT1: std_logic;
signal CLKOUT2: std_logic;
signal CLKOUT0G_LOCAL: std_logic;

--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
begin


  -- Input buffering
  --------------------------------------
  -- Global clock input buffer. The PLL will compensate the delay of this path (ug382)
  IBUFG_001: IBUFG port map
   (O => CLKREF_INB,
    I => CLKREF_IN);


  -- Clocking primitive
  --------------------------------------
  -- Instantiation of the PLL primitive
  --    * Unused inputs are tied off
  --    * Unused outputs are labeled unused

  pll_base_inst : PLL_BASE
  generic map
   (BANDWIDTH            => "OPTIMIZED",
    CLK_FEEDBACK         => "CLKOUT0",
    COMPENSATION         => "SYSTEM_SYNCHRONOUS",
    DIVCLK_DIVIDE        => 1,	
    CLKFBOUT_MULT        => 1,	
    CLKFBOUT_PHASE       => 0.000,
    CLKOUT0_DIVIDE       => 12,	-- 60 MHz output. VCO 720 MHz
    CLKOUT0_PHASE        => 0.0,
    CLKOUT0_DUTY_CYCLE   => 0.500,
    CLKOUT1_DIVIDE       => 6,	-- CLK_P 120 MHz output
    CLKOUT1_PHASE        => 0.000,
    CLKOUT1_DUTY_CYCLE   => 0.500,
    CLKOUT2_DIVIDE       => 6,	-- CLK_DDR2: DDR2 SDRAM CLK 120 MHz output
    CLKOUT2_PHASE        => 0.0,
    CLKOUT2_DUTY_CYCLE   => 0.500,
    CLKIN_PERIOD         => 16.666,
    REF_JITTER           => 0.010)
  port map
    -- Output clocks
   (CLKFBOUT            => open,
    CLKOUT0             => CLKOUT0,
    CLKOUT1             => CLKOUT1,
    CLKOUT2             => CLKOUT2,
    CLKOUT3             => open,
    CLKOUT4             => open,
    CLKOUT5             => open,
    -- Status and control signals
    LOCKED              => LOCKED_PLL,
    RST                 => '0',
    -- Input clock control
    CLKFBIN             => CLKOUT0G_LOCAL,
    CLKIN               => CLKREF_INB);

  -- Output buffering
  -------------------------------------
BUFG_000: BUFG port map(I => CLKOUT0, O => CLKOUT0G_LOCAL);
BUFG_001: BUFG port map(I => CLKOUT1, O => CLKOUT1G);
BUFG_002: BUFG port map(I => CLKOUT2, O => CLKOUT2G);

CLKOUT0G <= CLKOUT0G_LOCAL;



end Behavioral;
