--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:32:31 08/12/2011
-- Design Name:   
-- Module Name:   C:/Users/Alain/Documents/source_VHDL/com-5402_002work/sim/tbstream_2_packets.vhd
-- Project Name:  com1600_ise131
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: STREAM_2_PACKETS
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
 
ENTITY tbstream_2_packets IS
END tbstream_2_packets;
 
ARCHITECTURE behavior OF tbstream_2_packets IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT STREAM_2_PACKETS
	generic (
		NBUFS: integer
	);
    PORT(
         ASYNC_RESET : IN  std_logic;
         CLK : IN  std_logic;
         TICK_4US : IN  std_logic;
         STREAM_DATA : IN  std_logic_vector(7 downto 0);
         STREAM_DATA_VALID : IN  std_logic;
         STREAM_CTS : OUT  std_logic;
         DATA_OUT : OUT  std_logic_vector(7 downto 0);
         DATA_VALID_OUT : OUT  std_logic;
         SOF_OUT : OUT  std_logic;
         EOF_OUT : OUT  std_logic;
         CTS_IN : IN  std_logic;
         ACK_IN : IN  std_logic;
         NAK_IN : IN  std_logic;
         TP : OUT  std_logic_vector(10 downto 1)
        );
    END COMPONENT;
    

   --Inputs
   signal ASYNC_RESET : std_logic := '0';
   signal CLK : std_logic := '0';
   signal TICK_4US : std_logic := '0';
   signal STREAM_DATA : std_logic_vector(7 downto 0) := (others => '0');
   signal STREAM_DATA_VALID : std_logic := '0';
   signal CTS_IN : std_logic := '0';
   signal ACK_IN : std_logic := '0';
   signal NAK_IN : std_logic := '0';

 	--Outputs
   signal STREAM_CTS : std_logic;
   signal DATA_OUT : std_logic_vector(7 downto 0);
   signal DATA_VALID_OUT : std_logic;
   signal SOF_OUT : std_logic;
   signal EOF_OUT : std_logic;
   signal TP : std_logic_vector(10 downto 1);

   -- Clock period definitions
   constant CLK_period : time := 8 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: STREAM_2_PACKETS 
	GENERIC MAP(
		NBUFS => 1
	)
	PORT MAP (
          ASYNC_RESET => ASYNC_RESET,
          CLK => CLK,
          TICK_4US => TICK_4US,
          STREAM_DATA => STREAM_DATA,
          STREAM_DATA_VALID => STREAM_DATA_VALID,
          STREAM_CTS => STREAM_CTS,
          DATA_OUT => DATA_OUT,
          DATA_VALID_OUT => DATA_VALID_OUT,
          SOF_OUT => SOF_OUT,
          EOF_OUT => EOF_OUT,
          CTS_IN => CTS_IN,
          ACK_IN => ACK_IN,
          NAK_IN => NAK_IN,
          TP => TP
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
	TICK: process
	begin
		TICK_4US <= '0';
		wait for 100ns;
		TICK_4US <= '1';
		wait for 8ns;
	end process;
	
	CTS_IN <= '1';
	ACK_IN <= '0';
	--NAK_IN <= '0';
	
	STREAM_GEN: process(CLK)
	begin
		if rising_edge(CLK) then
			if(TICK_4US = '1') then
				STREAM_DATA_VALID <= '1';
				STREAM_DATA <= STREAM_DATA + 1;
			else
				STREAM_DATA_VALID <= '0';
			end if;
		end if;
	end process;

	NAK_001: process
	begin
		NAK_IN <= '0';
		wait for 150ns;
		NAK_IN <= '1';
		wait for 8ns;
	end process;

END;
