--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   10:10:15 07/29/2011
-- Design Name:   
-- Module Name:   C:/Users/Alain/Documents/source_VHDL/com-5402_000/sim/tbarp_cache2.vhd
-- Project Name:  com5402_ISE131
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ARP_CACHE2
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tbarp_cache2 IS
END tbarp_cache2;
 
ARCHITECTURE behavior OF tbarp_cache2 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
	COMPONENT ARP_CACHE2
	PORT(
		ASYNC_RESET : IN std_logic;
		CLK : IN std_logic;
		TICK_100MS : IN std_logic;
		RT_IP_ADDR : IN std_logic_vector(31 downto 0);
		RT_REQ_RTS : IN std_logic;
		MAC_ADDR : IN std_logic_vector(47 downto 0);
		IPv4_ADDR : IN std_logic_vector(31 downto 0);
		SUBNET_MASK : IN std_logic_vector(31 downto 0);
		GATEWAY_IP_ADDR : IN std_logic_vector(31 downto 0);
		RX_SOURCE_ADDR_RDY : IN std_logic;
		RX_SOURCE_MAC_ADDR : IN std_logic_vector(47 downto 0);
		RX_SOURCE_IP_ADDR : IN std_logic_vector(31 downto 0);          
		RT_CTS : OUT std_logic;
		RT_MAC_REPLY : OUT std_logic_vector(47 downto 0);
		RT_MAC_RDY : OUT std_logic;
		RT_NAK : OUT std_logic;
		WHOIS_IP_ADDR : OUT std_logic_vector(31 downto 0);
		WHOIS_START : OUT std_logic;
		SREG1 : OUT std_logic_vector(7 downto 0);
		SREG2 : OUT std_logic_vector(7 downto 0);
		SREG3 : OUT std_logic_vector(7 downto 0);
		SREG4 : OUT std_logic_vector(7 downto 0);
		SREG5 : OUT std_logic_vector(7 downto 0);
		SREG6 : OUT std_logic_vector(7 downto 0);
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal ASYNC_RESET : std_logic := '0';
   signal RT_IP_ADDR : std_logic_vector(31 downto 0) := x"7F000001";
   signal RT_REQ_RTS : std_logic := '0';
   signal IPv4_ADDR : std_logic_vector(31 downto 0) := x"AC100180";
   signal SUBNET_MASK : std_logic_vector(31 downto 0) := x"FFFFFF00";
   signal GATEWAY_IP_ADDR : std_logic_vector(31 downto 0) := x"AC100102";
   signal RX_SOURCE_ADDR_RDY : std_logic := '0';
   signal RX_SOURCE_MAC_ADDR : std_logic_vector(47 downto 0) := (others => '0');
   signal RX_SOURCE_IP_ADDR : std_logic_vector(31 downto 0) := x"AC100101";
   signal TICK_100MS : std_logic := '0';

 	--Outputs
   signal RT_MAC_REPLY : std_logic_vector(47 downto 0);
   signal RT_MAC_RDY : std_logic;
   signal WHOIS_IP_ADDR : std_logic_vector(31 downto 0);
   signal WHOIS_START : std_logic;
   signal SREG1 : std_logic_vector(7 downto 0);
   signal SREG2 : std_logic_vector(7 downto 0);
   signal SREG3 : std_logic_vector(7 downto 0);
   signal SREG4 : std_logic_vector(7 downto 0);
   signal SREG5 : std_logic_vector(7 downto 0);
   signal SREG6 : std_logic_vector(7 downto 0);
   signal TP : std_logic_vector(10 downto 1);

   -- Clock period definitions
   constant CLK_period : time := 8 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ARP_CACHE2 PORT MAP (
          ASYNC_RESET => ASYNC_RESET,
          CLK => CLK,
          TICK_100MS => TICK_100MS,
          RT_IP_ADDR => RT_IP_ADDR,
          RT_REQ_RTS => RT_REQ_RTS,
			 RT_CTS => open,
          RT_MAC_REPLY => RT_MAC_REPLY,
          RT_MAC_RDY => RT_MAC_RDY,
			 RT_NAK => open,
			 MAC_ADDR => x"000102030405",
          IPv4_ADDR => IPv4_ADDR,
          SUBNET_MASK => SUBNET_MASK,
          GATEWAY_IP_ADDR => GATEWAY_IP_ADDR,
          WHOIS_IP_ADDR => WHOIS_IP_ADDR,
          WHOIS_START => WHOIS_START,
          RX_SOURCE_ADDR_RDY => RX_SOURCE_ADDR_RDY,
          RX_SOURCE_MAC_ADDR => RX_SOURCE_MAC_ADDR,
          RX_SOURCE_IP_ADDR => RX_SOURCE_IP_ADDR,
          SREG1 => SREG1,
          SREG2 => SREG2,
          SREG3 => SREG3,
          SREG4 => SREG4,
          SREG5 => SREG5,
          SREG6 => SREG6,
          TP => TP
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
process
begin
	RT_REQ_RTS <= '0';
	wait for 4200 ns;
	RT_REQ_RTS <= '1';
	wait for 8 ns;
	RT_REQ_RTS <= '0';
	wait;
end process;

process
begin
	TICK_100MS <= '0';
	wait for 100 ms;
	TICK_100MS <= '1';
	wait for 8 ns;
end process;

END;
