# Input clock periods. These duplicate the values entered for the
#  input clocks. You can use these to time your system
#----------------------------------------------------------------
NET "Inst_ddr2_sdram_controller_test/Inst_DDR2_SDRAM_CONTROLLER/Inst_CLKGEN_DCM/CLK_DDR2" TNM_NET = TNM_NET_CLK_DDR2_0;
NET "Inst_ddr2_sdram_controller_test/Inst_DDR2_SDRAM_CONTROLLER/Inst_CLKGEN_DCM/CLK_DDR2_90" TNM_NET = TNM_NET_CLK_DDR2_90;
TIMESPEC "TS_CLK_DDR2_0" = PERIOD "TNM_NET_CLK_DDR2_0" 7.69 ns HIGH 50%;
TIMESPEC "TS_CLK_DDR2_90" = PERIOD "TNM_NET_CLK_DDR2_90" 7.69 ns HIGH 50%;
# ignore constraints below because the code never reads back its own output signals (ISE tries
# to relate the output timing to the input timing, which is non-sensical)
NET "Inst_ddr2_sdram_controller_test/Inst_DDR2_SDRAM_CONTROLLER/SDRAM_DQS_IN<0>" TIG;
NET "Inst_ddr2_sdram_controller_test/Inst_DDR2_SDRAM_CONTROLLER/SDRAM_DQS_IN<1>" TIG;

############################################################################
#----------------------------------- DDR2 ----------------------------------
############################################################################
NET "SDRAM_DQ<*>"                            	IN_TERM = UNTUNED_SPLIT_50;
NET  "SDRAM_A<*>"                               OUT_TERM = UNTUNED_25;
NET  "SDRAM_BA<*>"                              OUT_TERM = UNTUNED_25;
NET  "SDRAM_RASN"                               OUT_TERM = UNTUNED_25;
NET  "SDRAM_CASN"                               OUT_TERM = UNTUNED_25;
NET  "SDRAM_WEN"                                OUT_TERM = UNTUNED_25;

NET  "SDRAM_DQS_P<0>"                           IOSTANDARD = DIFF_SSTL18_II;
NET  "SDRAM_DQS_P<1>"                           IOSTANDARD = DIFF_SSTL18_II;
NET  "SDRAM_DQS_N<0>"                           IOSTANDARD = DIFF_SSTL18_II;
NET  "SDRAM_DQS_N<1>"                           IOSTANDARD = DIFF_SSTL18_II;

#SSTL18_I unidirectional, SSTL18_II bidirectional
NET  "SDRAM_CK_P"                               IOSTANDARD = DIFF_SSTL18_II;
NET  "SDRAM_CK_N"                               IOSTANDARD = DIFF_SSTL18_II;
NET  "SDRAM_DQ<*>"                              IOSTANDARD = SSTL18_II;
NET  "SDRAM_A<*>"                               IOSTANDARD = SSTL18_I;
NET  "SDRAM_BA<*>"                              IOSTANDARD = SSTL18_I;
NET  "SDRAM_CKE"                                IOSTANDARD = SSTL18_I;
NET  "SDRAM_RASN"                               IOSTANDARD = SSTL18_I;
NET  "SDRAM_CASN"                               IOSTANDARD = SSTL18_I;
NET  "SDRAM_WEN"                                IOSTANDARD = SSTL18_I;
NET  "SDRAM_ODT"                                IOSTANDARD = SSTL18_I;
NET  "SDRAM_DM<0>"                              IOSTANDARD = SSTL18_I;
NET  "SDRAM_DM<1>"                              IOSTANDARD = SSTL18_I;
NET  "SDRAM_A<0>"                            LOC = "J7" ;
NET  "SDRAM_A<10>"                           LOC = "F4" ;
NET  "SDRAM_A<11>"                           LOC = "D3" ;
NET  "SDRAM_A<12>"                           LOC = "G6" ;
NET  "SDRAM_A<1>"                            LOC = "J6" ;
NET  "SDRAM_A<2>"                            LOC = "H5" ;
NET  "SDRAM_A<3>"                            LOC = "L7" ;
NET  "SDRAM_A<4>"                            LOC = "F3" ;
NET  "SDRAM_A<5>"                            LOC = "H4" ;
NET  "SDRAM_A<6>"                            LOC = "H3" ;
NET  "SDRAM_A<7>"                            LOC = "H6" ;
NET  "SDRAM_A<8>"                            LOC = "D2" ;
NET  "SDRAM_A<9>"                            LOC = "D1" ;
NET  "SDRAM_BA<0>"                           LOC = "F2" ;
NET  "SDRAM_BA<1>"                           LOC = "F1" ;
NET  "SDRAM_BA<2>"                           LOC = "E1" ;
NET  "SDRAM_CASN"                            LOC = "K5" ;
NET  "SDRAM_CK_P"                            LOC = "G3" ;
NET  "SDRAM_CK_N"                            LOC = "G1" ;
NET  "SDRAM_CKE"                             LOC = "H7" ;
NET  "SDRAM_DM<0>"                           LOC = "K3" ;
NET  "SDRAM_DQ<0>"                           LOC = "L2" ;
NET  "SDRAM_DQ<10>"                          LOC = "N2" ;
NET  "SDRAM_DQ<11>"                          LOC = "N1" ;
NET  "SDRAM_DQ<12>"                          LOC = "T2" ;
NET  "SDRAM_DQ<13>"                          LOC = "T1" ;
NET  "SDRAM_DQ<14>"                          LOC = "U2" ;
NET  "SDRAM_DQ<15>"                          LOC = "U1" ;
NET  "SDRAM_DQ<1>"                           LOC = "L1" ;
NET  "SDRAM_DQ<2>"                           LOC = "K2" ;
NET  "SDRAM_DQ<3>"                           LOC = "K1" ;
NET  "SDRAM_DQ<4>"                           LOC = "H2" ;
NET  "SDRAM_DQ<5>"                           LOC = "H1" ;
NET  "SDRAM_DQ<6>"                           LOC = "J3" ;
NET  "SDRAM_DQ<7>"                           LOC = "J1" ;
NET  "SDRAM_DQ<8>"                           LOC = "M3" ;
NET  "SDRAM_DQ<9>"                           LOC = "M1" ;
NET  "SDRAM_DQS_P<0>"                        LOC = "L4" ;
NET  "SDRAM_DQS_N<0>"                        LOC = "L3" ;
NET  "SDRAM_ODT"                             LOC = "K6" ;
NET  "SDRAM_RASN"                            LOC = "L5" ;
NET  "SDRAM_DM<1>"                           LOC = "K4" ;
NET  "SDRAM_DQS_P<1>"                        LOC = "P2" ;
NET  "SDRAM_DQS_N<1>"                        LOC = "P1" ;
NET  "SDRAM_WEN"                             LOC = "E3" ;
#always enabled NET  "SDRAM_CSB"                            		LOC = "" ;
INST "SDRAM_DQS_P<*>" TNM = SDRAM_OUT90;
INST "SDRAM_DQS_N<*>" TNM = SDRAM_OUT90;
TIMEGRP "SDRAM_OUT90" OFFSET = OUT 7.2 ns AFTER <name of external reference clock> RISING;

INST "SDRAM_CK_P" TNM = SDRAM_OUT0;
INST "SDRAM_CK_N" TNM = SDRAM_OUT0;
INST "SDRAM_A<*>" TNM = SDRAM_OUT0;
INST "SDRAM_BA<*>" TNM = SDRAM_OUT0;
INST "SDRAM_RASN" TNM = SDRAM_OUT0;
INST "SDRAM_CASN" TNM = SDRAM_OUT0;
INST "SDRAM_WEN" TNM = SDRAM_OUT0;
# output signals delay range 6.7 - 7.2 ns. See Data Sheet report within the 
# post PAR static timing report
TIMEGRP "SDRAM_OUT0" OFFSET = OUT 7.2 ns AFTER <name of external reference clock> RISING;