--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   10:42:08 07/23/2015
-- Design Name:   
-- Module Name:   C:/Users/Alain/Documents/1VHDL/com-1800_001j/src/DDR3/sim/tbDDR3_WRAPPER.vhd
-- Project Name:  com1800_ISE14
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DDR3_WRAPPER
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tbDDR3_WRAPPER IS
END tbDDR3_WRAPPER;
 
ARCHITECTURE behavior OF tbDDR3_WRAPPER IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DDR3_WRAPPER
	GENERIC (
		SIMULATION: std_logic
	);	
    PORT(
         CLK : IN  std_logic;
         SYNC_RESET : IN  std_logic;
         CLKREF_IN : IN  std_logic;
         DATA1_IN : IN  std_logic_vector(511 downto 0);
         DATA1_IN_VALID : IN  std_logic;
         DATA1_IN_CTS : OUT  std_logic;
         DATA1_IN_SETADDR : IN  std_logic;
         DATA1_IN_STARTADDR : IN  std_logic_vector(31 downto 0);
         DATA1_IN_CEILINGADDR : IN  std_logic_vector(31 downto 0);
         DATA1_IN_MODE : IN  std_logic_vector(1 downto 0);
         DATA1_OUT : OUT  std_logic_vector(511 downto 0);
         DATA1_OUT_VALID : OUT  std_logic;
         DATA1_OUT_CTS : IN  std_logic;
         DATA1_OUT_EMPTY : OUT  std_logic;
         DATA1_OUT_SETADDR : IN  std_logic;
         DATA1_OUT_STARTADDR : IN  std_logic_vector(31 downto 0);
         DATA1_OUT_CEILINGADDR : IN  std_logic_vector(31 downto 0);
         DATA1_OUT_MODE : IN  std_logic_vector(1 downto 0);
         DATA1_IN_ADDR : OUT  std_logic_vector(31 downto 0);
         DATA1_OUT_ADDR : OUT  std_logic_vector(31 downto 0);
         ddr3_dq : INOUT  std_logic_vector(63 downto 0);
         ddr3_dqs_p : INOUT  std_logic_vector(7 downto 0);
         ddr3_dqs_n : INOUT  std_logic_vector(7 downto 0);
         ddr3_addr : OUT  std_logic_vector(15 downto 0);
         ddr3_ba : OUT  std_logic_vector(2 downto 0);
         ddr3_ras_n : OUT  std_logic;
         ddr3_cas_n : OUT  std_logic;
         ddr3_we_n : OUT  std_logic;
         ddr3_reset_n : OUT  std_logic;
         ddr3_ck_p : OUT  std_logic_vector(0 downto 0);
         ddr3_ck_n : OUT  std_logic_vector(0 downto 0);
         ddr3_cke : OUT  std_logic_vector(0 downto 0);
         ddr3_cs_n : OUT  std_logic_vector(0 downto 0);
         ddr3_dm : OUT  std_logic_vector(7 downto 0);
         ddr3_odt : OUT  std_logic_vector(0 downto 0);
         PLL_LOCKED_OUT : OUT  std_logic;
			MEMORY_RDY_OUT: out std_logic;
			TP : OUT  std_logic_vector(10 downto 1)
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal SYNC_RESET : std_logic := '0';
   signal CLKREF_IN : std_logic := '0';
   signal DATA1_IN : std_logic_vector(511 downto 0) := (others => '0');
   signal DATA1_IN_VALID : std_logic := '0';
   signal DATA1_IN_SETADDR : std_logic := '0';
   signal DATA1_IN_STARTADDR : std_logic_vector(31 downto 0) := (others => '0');
   signal DATA1_IN_CEILINGADDR : std_logic_vector(31 downto 0) := (others => '0');
   signal DATA1_IN_MODE : std_logic_vector(1 downto 0) := (others => '0');
   signal DATA1_OUT_CTS : std_logic := '0';
   signal DATA1_OUT_SETADDR : std_logic := '0';
   signal DATA1_OUT_STARTADDR : std_logic_vector(31 downto 0) := (others => '0');
   signal DATA1_OUT_CEILINGADDR : std_logic_vector(31 downto 0) := (others => '0');
   signal DATA1_OUT_MODE : std_logic_vector(1 downto 0) := (others => '0');

	--BiDirs
   signal ddr3_dq : std_logic_vector(63 downto 0);
   signal ddr3_dqs_p : std_logic_vector(7 downto 0);
   signal ddr3_dqs_n : std_logic_vector(7 downto 0);

 	--Outputs
   signal DATA1_IN_CTS : std_logic;
   signal DATA1_OUT : std_logic_vector(511 downto 0);
   signal DATA1_OUT_VALID : std_logic;
   signal DATA1_OUT_EMPTY : std_logic;
   signal DATA1_IN_ADDR : std_logic_vector(31 downto 0);
   signal DATA1_OUT_ADDR : std_logic_vector(31 downto 0);
   signal ddr3_addr : std_logic_vector(15 downto 0);
   signal ddr3_ba : std_logic_vector(2 downto 0);
   signal ddr3_ras_n : std_logic;
   signal ddr3_cas_n : std_logic;
   signal ddr3_we_n : std_logic;
   signal ddr3_reset_n : std_logic;
   signal ddr3_ck_p : std_logic_vector(0 downto 0);
   signal ddr3_ck_n : std_logic_vector(0 downto 0);
   signal ddr3_cke : std_logic_vector(0 downto 0);
   signal ddr3_cs_n : std_logic_vector(0 downto 0);
   signal ddr3_dm : std_logic_vector(7 downto 0);
   signal ddr3_odt : std_logic_vector(0 downto 0);
   signal PLL_LOCKED_OUT : std_logic;
	signal MEMORY_RDY_OUT: std_logic;
	signal DDR3_TP : std_logic_vector(10 downto 1);

   -- Clock period definitions
   constant CLK_period : time := 8 ns;
   constant CLKREF_IN_period : time := 52.083 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DDR3_WRAPPER 
	GENERIC MAP(
			SIMULATION => '1'
	)
	PORT MAP (
          CLK => CLK,
          SYNC_RESET => SYNC_RESET,
          CLKREF_IN => CLKREF_IN,
          DATA1_IN => DATA1_IN,
          DATA1_IN_VALID => DATA1_IN_VALID,
          DATA1_IN_CTS => DATA1_IN_CTS,
          DATA1_IN_SETADDR => DATA1_IN_SETADDR,
          DATA1_IN_STARTADDR => DATA1_IN_STARTADDR,
          DATA1_IN_CEILINGADDR => DATA1_IN_CEILINGADDR,
          DATA1_IN_MODE => DATA1_IN_MODE,
          DATA1_OUT => DATA1_OUT,
          DATA1_OUT_VALID => DATA1_OUT_VALID,
          DATA1_OUT_CTS => DATA1_OUT_CTS,
          DATA1_OUT_EMPTY => DATA1_OUT_EMPTY,
          DATA1_OUT_SETADDR => DATA1_OUT_SETADDR,
          DATA1_OUT_STARTADDR => DATA1_OUT_STARTADDR,
          DATA1_OUT_CEILINGADDR => DATA1_OUT_CEILINGADDR,
          DATA1_OUT_MODE => DATA1_OUT_MODE,
          DATA1_IN_ADDR => DATA1_IN_ADDR,
          DATA1_OUT_ADDR => DATA1_OUT_ADDR,
          ddr3_dq => ddr3_dq,
          ddr3_dqs_p => ddr3_dqs_p,
          ddr3_dqs_n => ddr3_dqs_n,
          ddr3_addr => ddr3_addr,
          ddr3_ba => ddr3_ba,
          ddr3_ras_n => ddr3_ras_n,
          ddr3_cas_n => ddr3_cas_n,
          ddr3_we_n => ddr3_we_n,
          ddr3_reset_n => ddr3_reset_n,
          ddr3_ck_p => ddr3_ck_p,
          ddr3_ck_n => ddr3_ck_n,
          ddr3_cke => ddr3_cke,
          ddr3_cs_n => ddr3_cs_n,
          ddr3_dm => ddr3_dm,
          ddr3_odt => ddr3_odt,
          PLL_LOCKED_OUT => PLL_LOCKED_OUT,
			 MEMORY_RDY_OUT => MEMORY_RDY_OUT,
			 TP => DDR3_TP
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
   CLKREF_IN_process :process
   begin
		CLKREF_IN <= '0';
		wait for CLKREF_IN_period/2;
		CLKREF_IN <= '1';
		wait for CLKREF_IN_period/2;
   end process;
 
   ASYNC_proc: process
   begin	
		SYNC_RESET <= '1';
		wait for 1us;
		SYNC_RESET <= '0';
		wait;
   end process;
	
	-- write transaction
	WR_001: process
	begin
		DATA1_IN <= (others => '0');
		DATA1_IN_VALID <= '0';
		DATA1_IN_SETADDR <= '0';
		DATA1_IN_STARTADDR <= (others => '0');
		DATA1_IN_CEILINGADDR <= (others => '0');
		DATA1_IN_MODE <= (others => '0');
		wait until (MEMORY_RDY_OUT = '1');
		DATA1_IN_SETADDR <= '1';
		DATA1_IN_STARTADDR <= x"0000000a";
		DATA1_IN_CEILINGADDR <= x"0000000c";
		DATA1_IN_MODE <= "00";
		wait for 8 ns;
		DATA1_IN_SETADDR <= '0';
		DATA1_IN <= x"000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f202122232425262728292a2b2c2d2e2f303132333435363738393a3b3c3d3e3f";
		DATA1_IN_VALID <= '1';
		wait for 8 ns;
		DATA1_IN_SETADDR <= '0';
		DATA1_IN(511 downto 504) <= x"01";
		DATA1_IN_VALID <= '1';
		wait for 8 ns;
		DATA1_IN_SETADDR <= '0';
		DATA1_IN(511 downto 504) <= x"02";
		DATA1_IN_VALID <= '1';
		wait for 8 ns;
		DATA1_IN_SETADDR <= '0';
		DATA1_IN(511 downto 504) <= x"03";
		DATA1_IN_VALID <= '1';
		wait for 8 ns;
		DATA1_IN_SETADDR <= '0';
		DATA1_IN(511 downto 504) <= x"04";
		DATA1_IN_VALID <= '1';
		wait for 8 ns;
		DATA1_IN <= (others => '0');
		DATA1_IN_VALID <= '0';
		wait;
	end process;
		
	-- read transaction
	RD_001: process
	begin
		DATA1_OUT_CTS <= '1';
		DATA1_OUT_SETADDR <= '0';
		DATA1_OUT_STARTADDR <= (others => '0');
		DATA1_OUT_CEILINGADDR <= (others => '0');
		DATA1_OUT_MODE <= (others => '0');
		wait until (MEMORY_RDY_OUT = '1');
		DATA1_OUT_SETADDR <= '1';
		DATA1_OUT_STARTADDR <= x"0000000a";
		DATA1_OUT_CEILINGADDR <= x"0000000c";
		DATA1_OUT_MODE <= "01";
		wait for 8 ns;
		DATA1_OUT_SETADDR <= '0';
		wait for 10us;
		DATA1_OUT_SETADDR <= '1';
		DATA1_OUT_MODE <= "11";
		wait for 8 ns;
		DATA1_OUT_SETADDR <= '0';
		
		wait;
	end process;
		
		
	

END;
