-------------------------------------------------------------
-- MSS copyright 2015
-- Filename:  COM1800_TOP.VHD
-- Authors: 
--		Alain Zarembowitch / MSS
-- Version: Rev 2i
-- Last modified: 12/9/15
-- Inheritance: 	n/a
--
-- description:  Top level for COM-1800 FPGA development platform REV2 ONLY
-- Use as framework for new project.
-- Control registers CREGxx and Status registers SREGyy are accessed by the user through 
-- the ARM processor.
-- Via USB:  user <-- USB --> ARM <-- bus --> FPGA
-- Via LAN:  user <-- LAN/TCP --> FPGA <-- bus --> ARM <-- bus --> FPGA
-- The control registers are stored in non-volatile (flash) memory within the ARM coprocessor and 
-- (re)loaded automatically at power up or reset.
-- Users can define control registers as needed (up to 230) by modifying the UC_WRITE_001 process within.
-- Users can define status registers as needed by modifying the UC_READ_001 process within.
-- The DDR3 SODIMM memory interface controller is generated using Xilinx IP: MIG 7 series version 2.3
-- It requires the use of the latest Vivado tools (2015.2 or above)
---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.com5402pkg.all;	-- defines global types, number of TCP streams, etc
Library UNISIM;
use UNISIM.vcomponents.all;

entity COM1800_TOP is
	generic (
		OPTION: std_logic_vector(7 downto 0) := x"41";    -- 'A'    -- internal VCTCXO frequency reference 19.2MHz
		--OPTION: std_logic_vector(7 downto 0) := x"42";    -- 'B'    -- external 10 MHz frequency reference  
		REVISION: std_logic_vector(7 downto 0) := x"31";    -- '1'
		--// FPGA option and revision (ASCII format '0' = x30, 'A' = x41)
		-- These two ASCII characters appear in the Comblock Control Center.
		-- Helpful in identifying which firmware version is currently running in the FPGA. 
		-- Select internal vs external frequency reference option. 
		-- REMINDER: do change the .xdc file according to the option selection -A or -B
		DDR3_NRANKS: integer := 1;	-- number of ranks , range 1-2
		DDR3_NADDRBITS: integer := 14;	
			-- number of address bits, in accordance with memory size 14(1GB),16(4GB),17(8GB)
			-- MIG must be configured accordingly
		APP_NADDRBITS: integer := 28;	
			-- number of application address bits (address of 64-bit words), 
			-- in accordance with memory size 28(1GB),30(4GB),??(8GB)
		SIMULATION: std_logic := '0'
		-- 1 during simulation, 0 for release	
	);
    Port ( 
		--GLOBAL CLOCKS
	   CLKREF_TCXO : in std_logic;	
			-- 19.2MHz reference clock. Generated by the VCTCXO on this board.
		CLKREF25B: in std_logic;
			-- 25 MHz low-jitter, but poor stability
		CLKREF_EXT: in std_logic;
			-- external (higher-stability) frequency reference via J9 SMA connector ("EXT REF")

        --// GbE LAN. 
        -- connects to RGMII PHY (Micrel KSZ9031)
		LAN_TXC: out std_logic;  -- tx clock
		LAN_TXD: out std_logic_vector(3 downto 0);  -- tx data
		LAN_TX_CTL: out std_logic;  -- tx control: combines TX_EN and TX_ER
			-- valid at the falling clock edge
		LAN_RXC: in std_logic;  -- receive clock
			-- must be delayed by 1.5 to 2.1 ns to prevent glitches
			-- Set the strapping options in the .ucf constraint file.
		LAN_RXD: in std_logic_vector(3 downto 0);  
			-- receive data
			-- Set the strapping options in the .ucf constraint file.
		LAN_RX_CTL: in std_logic;  -- receive control. combines RX_DV and RX_ER
			-- valid at the falling clock edge
			-- Note: Micrel KSZ9021RN PHY defines these as dual-function signals.
			-- Set the strapping options in the .ucf constraint file.
		LAN_RESET_N: out std_logic;
			-- PHY reset
		LAN_MCLK: out std_logic;
		LAN_MDIO: inout std_logic;  -- (tri-state)
		LAN_CLK125: in std_logic;   -- optional 125 MHz from PHY
		LAN_INT_N: in std_logic;    -- unused interrupt

		--// DDR3 SDRAM SODIMM. 1.5 V
		-- Inouts
		ddr3_dq                        : inout std_logic_vector(63 downto 0);
		ddr3_dqs_p                     : inout std_logic_vector(7 downto 0);
		ddr3_dqs_n                     : inout std_logic_vector(7 downto 0);

		-- Outputs
		ddr3_addr                      : out   std_logic_vector((DDR3_NADDRBITS-1) downto 0);
		ddr3_ba                        : out   std_logic_vector(2 downto 0);
		ddr3_ras_n                     : out   std_logic;
		ddr3_cas_n                     : out   std_logic;
		ddr3_we_n                      : out   std_logic;
		ddr3_reset_n                   : out   std_logic;
		ddr3_ck_p                      : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_ck_n                      : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_cke                       : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_cs_n                      : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_odt                       : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_dm                        : out   std_logic_vector(7 downto 0);
 
		-- 4 XAUI pairs for future connection to 10gbase-T Ethernet PHY
		-- TODO
 
		--// Left connector, 98 pin PCIe female connector. 
		-- Pins B5,B20,B31,B42 reserved for Ground
		-- Pins A49/B49 reserved for ComBlock Monitoring and Control.
		-- Place B13 in high-impedance when using the 12-bit DAC or vice versa.
		-- Hardware connects LEFT_CONNECTOR_A(38:32) with LEFT_CONNECTOR_B2(16:10)
		LEFT_CONNECTOR_A: inout std_logic_vector(38 downto 1);
		LEFT_CONNECTOR_B1: inout std_logic_vector(4 downto 1);
		LEFT_CONNECTOR_B2: inout std_logic_vector(16 downto 6);

		--// Right connector: 98 pin PCIe female connector.   
		-- Pins B5,B20,B31,B42 reserved for Ground
		-- Pins A49/B49 reserved for ComBlock Monitoring and Control.
		-- Connector pins A39 - A48, B40,B41,B43-B48 can be used by 
		-- re-routing LEFT_CONNECTOR signals using a resistor array (requires soldering)
		-- See schematics for details.
		RIGHT_CONNECTOR_A: inout std_logic_vector(38 downto 1);
		RIGHT_CONNECTOR_B1: inout std_logic_vector(4 downto 1);
		RIGHT_CONNECTOR_B2: inout std_logic_vector(19 downto 6);
		RIGHT_CONNECTOR_B3: inout std_logic_vector(30 downto 21);
		RIGHT_CONNECTOR_B4: inout std_logic_vector(39 downto 32);

		--// Monitoring & Control: ARM Cortex M3 microcontroller interface
		-- asynchronous bus (shared with NAND flash)
		-- set address at the rising edge of UC_WEB_IN when UC_CSIB_IN = '0' and UC_ALE_IN = '1'
		-- write data the rising edge of UC_WEB_IN when UC_CSIB_IN = '0'
		-- read data when  UC_CSIB_IN = '0' and UC_REB_IN = '0'
		UC_CSIB_IN: in std_logic;  -- chip select. active low.
		UC_ALE_IN: in std_logic;  -- address latch enable. active high.
		UC_REB_IN: in std_logic;  -- read enable #
		UC_WEB_IN: in std_logic;	-- write enable #
		UC_AD: inout std_logic_vector(7 downto 0)  -- shared address/data bus

		  
			  );
end entity;

architecture Behavioral of COM1800_TOP is
--------------------------------------------------------
--      COMPONENTS
--------------------------------------------------------
-- Comment in/out components/drivers as needed

	COMPONENT CLKGEN7_MMCM_ADJ
	GENERIC (
        CLKFBOUT_MULT_F: real;
        CLKOUT0_DIVIDE_F: real;
        CLKIN1_PERIOD: real
    );    
    PORT(
        CLK_IN1 : IN std_logic;
        CLK_OUT1 : OUT std_logic;
        INPUT_CLK_STOPPED : OUT std_logic;
        LOCKED : OUT std_logic
        );
    END COMPONENT;

	COMPONENT TIMER_4US
	GENERIC (
		CLK_FREQUENCY: integer 
	);
	PORT(
		ASYNC_RESET : IN std_logic;
		CLK : IN std_logic;          
		TICK_4US : OUT std_logic;
		TICK_100MS: out std_logic
		);
	END COMPONENT;

	COMPONENT COM5401
	GENERIC (
		MII_SEL: std_logic;  
		PHY_ADDR: std_logic_vector(4 downto 0);
		CLK_FREQUENCY: integer; 
		PLATFORM: integer;
		TARGET_PHY: integer;
		INTERNAL_PHY_CLKS_DELAYS: std_logic;
		SIMULATION: std_logic
	);
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		MAC_TX_CONFIG : IN std_logic_vector(15 downto 0);
		MAC_RX_CONFIG : IN std_logic_vector(15 downto 0);
		MAC_ADDR : IN std_logic_vector(47 downto 0);
		PHY_CONFIG_CHANGE : IN std_logic;
		PHY_RESET : IN std_logic;
		SPEED : IN std_logic_vector(1 downto 0);
		DUPLEX : IN std_logic;
		TEST_MODE : IN std_logic_vector(1 downto 0);
		POWER_DOWN : IN std_logic;
		CLK_SKEW1: in std_logic_vector(15 downto 0);
		CLK_SKEW2: in std_logic_vector(15 downto 0);
		MAC_TX_DATA : IN std_logic_vector(7 downto 0);
		MAC_TX_DATA_VALID : IN std_logic;
		MAC_TX_EOF : IN std_logic;
		MAC_RX_CTS : IN std_logic;
		RXC : IN std_logic;
		RXD : IN std_logic_vector(3 downto 0);
		RX_CTL : IN std_logic;
		MII_TX_CLK : IN std_logic;
		GMII_MII_CRS : IN std_logic;
		GMII_MII_COL : IN std_logic;
		GMII_MII_RX_CLK : IN std_logic;
		GMII_MII_RXD : IN std_logic_vector(7 downto 0);
		GMII_MII_RX_DV : IN std_logic;
		GMII_MII_RX_ER : IN std_logic;    
		MDIO : INOUT std_logic;      
		MAC_TX_CTS : OUT std_logic;
		MAC_RX_DATA : OUT std_logic_vector(7 downto 0);
		MAC_RX_DATA_VALID : OUT std_logic;
		MAC_RX_SOF : OUT std_logic;
		MAC_RX_EOF : OUT std_logic;
		TXC : OUT std_logic;
		TXD : OUT std_logic_vector(3 downto 0);
		TX_CTL : OUT std_logic;
		RESET_N : OUT std_logic;
		MCLK : OUT std_logic;
		GMII_TX_CLK : OUT std_logic;
		GMII_MII_TXD : OUT std_logic_vector(7 downto 0);
		GMII_MII_TX_EN : OUT std_logic;
		GMII_MII_TX_ER : OUT std_logic;
		LINK_STATUS : OUT std_logic;
		SPEED_STATUS : OUT std_logic_vector(1 downto 0);
		DUPLEX_STATUS : OUT std_logic;
		PHY_ID: out std_logic_vector(15 downto 0);
		N_RX_FRAMES: out  std_logic_vector(15 downto 0);
		N_RX_BAD_CRCS: out  std_logic_vector(15 downto 0);
		N_RX_FRAMES_TOO_SHORT: out  std_logic_vector(15 downto 0);
		N_RX_FRAMES_TOO_LONG: out  std_logic_vector(15 downto 0);
		N_RX_WRONG_ADDR: out  std_logic_vector(15 downto 0);
		N_RX_LENGTH_ERRORS: out  std_logic_vector(15 downto 0);
		CS_CLKG: out std_logic;	
		CS1: out std_logic_vector(7 downto 0);
		CS1_CLK: out std_logic;
		CS2: out std_logic_vector(7 downto 0);
		CS2_CLK: out std_logic;
		CT1: out std_logic;
		CT1_CLK: out std_logic;
		TP: out std_logic_vector(10 downto 1)
		);
	END COMPONENT;

	COMPONENT COM5402
	GENERIC (
		NUDPTX: integer range 0 to 1;
		NUDPRX: integer range 0 to 1;
		NTCPSTREAMS: integer range 0 to 255;  
		CLK_FREQUENCY: integer;
		TX_IDLE_TIMEOUT: integer range 0 to 50;	
		SIMULATION: std_logic
	);	
	PORT(
		CLK : IN std_logic;
		ASYNC_RESET: in std_logic;
		SYNC_RESET: in std_logic;
		MAC_ADDR : IN std_logic_vector(47 downto 0);
		IPv4_ADDR : IN std_logic_vector(31 downto 0);
		IPv6_ADDR : IN std_logic_vector(127 downto 0);
		SUBNET_MASK: in std_logic_vector(31 downto 0);
		MULTICAST_IP_ADDR: in std_logic_vector(31 downto 0); 
		GATEWAY_IP_ADDR: in std_logic_vector(31 downto 0);
		CONNECTION_RESET: in std_logic_vector((NTCPSTREAMS-1) downto 0);
		MAC_TX_CTS : IN std_logic;
		MAC_RX_DATA : IN std_logic_vector(7 downto 0);
		MAC_RX_DATA_VALID : IN std_logic;
		MAC_RX_SOF : IN std_logic;
		MAC_RX_EOF : IN std_logic;          
		MAC_TX_DATA : OUT std_logic_vector(7 downto 0);
		MAC_TX_DATA_VALID : OUT std_logic;
		MAC_TX_SOF: out std_logic;
		MAC_TX_EOF : OUT std_logic;
		UDP_RX_DATA: out std_logic_vector(7 downto 0);
		UDP_RX_DATA_VALID: out std_logic;
		UDP_RX_SOF: out std_logic;	
		UDP_RX_EOF: out std_logic;	
		UDP_RX_DEST_PORT_NO_IN: in std_logic_vector(15 downto 0);
		CHECK_UDP_RX_DEST_PORT_NO: in std_logic;
		UDP_RX_DEST_PORT_NO_OUT: out std_logic_vector(15 downto 0);
		UDP_TX_DATA : IN std_logic_vector(7 downto 0);
		UDP_TX_DATA_VALID : IN std_logic;
		UDP_TX_SOF : IN std_logic;
		UDP_TX_EOF : IN std_logic;
		UDP_TX_CTS: out std_logic;	
		UDP_TX_ACK: out std_logic;	
		UDP_TX_NAK: out std_logic;	
		UDP_TX_DEST_IP_ADDR: in std_logic_vector(127 downto 0);
		UDP_TX_DEST_PORT_NO: in std_logic_vector(15 downto 0);
		UDP_TX_SOURCE_PORT_NO: in std_logic_vector(15 downto 0);
		TCP_RX_DATA: out SLV8xNTCPSTREAMStype;
		TCP_RX_DATA_VALID: out std_logic_vector((NTCPSTREAMS-1) downto 0);
		TCP_RX_RTS: out std_logic_vector((NTCPSTREAMS-1) downto 0);	
		TCP_RX_CTS: in std_logic_vector((NTCPSTREAMS-1) downto 0);	
		TCP_TX_DATA: in SLV8xNTCPSTREAMStype;
		TCP_TX_DATA_VALID: in std_logic_vector((NTCPSTREAMS-1) downto 0);
		TCP_TX_CTS: out std_logic_vector((NTCPSTREAMS-1) downto 0);	
		CS1 : OUT std_logic_vector(7 downto 0);
		CS1_CLK : OUT std_logic;
		CS2 : OUT std_logic_vector(7 downto 0);
		CS2_CLK : OUT std_logic;
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;
	
	COMPONENT ELASTIC_BUFFER_NRAMB
	GENERIC (
		NRAMB: integer;
		NBITS: integer;
		READ_AHEAD_1ADDRESS: std_logic
	);	
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATA_IN : IN std_logic_vector(8 downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		SAMPLE_CLK_OUT_REQ : IN std_logic;          
		SAMPLE_CLK_IN_REQ : OUT std_logic;
		DATA_OUT : OUT std_logic_vector(8 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic;
		SAMPLE_CLK_OUT_E : OUT std_logic;
		BUFFER_EMPTY: out std_logic
		);
	END COMPONENT;

	COMPONENT DDR3_WRAPPER
	GENERIC (
		DDR3_NRANKS: integer;
		DDR3_NADDRBITS: integer;
		APP_NADDRBITS: integer;	
		SIMULATION: std_logic
	);	
	PORT(
		CLK : IN  std_logic;
		SYNC_RESET : IN  std_logic;
		CLKREF_IN : IN  std_logic;
		DATA1_IN : IN  std_logic_vector(511 downto 0);
		DATA1_IN_VALID : IN  std_logic;
		DATA1_IN_CTS : OUT  std_logic;
		DATA1_IN_SETADDR : IN  std_logic;
		DATA1_IN_STARTADDR : IN  std_logic_vector(31 downto 0);
		DATA1_IN_CEILINGADDR : IN  std_logic_vector(31 downto 0);
		DATA1_IN_MODE : IN  std_logic_vector(1 downto 0);
		WRITE_COMMAND_COMPLETE: out std_logic;
		DATA1_OUT : OUT  std_logic_vector(511 downto 0);
		DATA1_OUT_VALID : OUT  std_logic;
		DATA1_OUT_CTS : IN  std_logic;
		DATA1_OUT_EMPTY : OUT  std_logic;
		DATA1_OUT_SETADDR : IN  std_logic;
		DATA1_OUT_STARTADDR : IN  std_logic_vector(31 downto 0);
		DATA1_OUT_CEILINGADDR : IN  std_logic_vector(31 downto 0);
		DATA1_OUT_MODE : IN  std_logic_vector(1 downto 0);
		DATA1_IN_ADDR : OUT  std_logic_vector(31 downto 0);
		DATA1_OUT_ADDR : OUT  std_logic_vector(31 downto 0);
		ddr3_dq : INOUT  std_logic_vector(63 downto 0);
		ddr3_dqs_p : INOUT  std_logic_vector(7 downto 0);
		ddr3_dqs_n : INOUT  std_logic_vector(7 downto 0);
		ddr3_addr : OUT  std_logic_vector((DDR3_NADDRBITS-1) downto 0);
		ddr3_ba : OUT  std_logic_vector(2 downto 0);
		ddr3_ras_n : OUT  std_logic;
		ddr3_cas_n : OUT  std_logic;
		ddr3_we_n : OUT  std_logic;
		ddr3_reset_n : OUT  std_logic;
		ddr3_ck_p : OUT  std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_ck_n : OUT  std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_cke : OUT  std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_cs_n : OUT  std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_odt : OUT  std_logic_vector((DDR3_NRANKS-1) downto 0);
		ddr3_dm : OUT  std_logic_vector(7 downto 0);
		PLL_LOCKED_OUT : OUT  std_logic;
		MEMORY_RDY_OUT: out std_logic;
		TP : OUT  std_logic_vector(20 downto 1)
	  );
	END COMPONENT;
	 
	COMPONENT MUXED_OUTPUT_2DDS
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATA_I_IN : IN std_logic_vector(15 downto 0);
		DATA_Q_IN : IN std_logic_vector(15 downto 0);
		TX_ENABLE_IN: in std_logic;
		DDS_CLK_IN : IN std_logic;          
		DATA_OUT : OUT std_logic_vector(15 downto 0);
		TX_ENABLE_OUT : OUT std_logic
		);
	END COMPONENT;

	COMPONENT DNA_ID
	GENERIC (
		CLK_FREQUENCY: integer
	);	
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;          
		ID_OUT : OUT std_logic_vector(56 downto 0) := (others => '0');
		ID_VALID_OUT : OUT std_logic;
		ID_SAMPLE_CLK_OUT : OUT std_logic
		);
	END COMPONENT;

	COMPONENT COMSCOPE2
	generic (
		TRACE1_ENABLED: std_logic;	
		TRACE2_ENABLED: std_logic;	
		TRACE3_ENABLED: std_logic;	
		TRACE4_ENABLED: std_logic;
		DATA_WIDTH1A: integer;
		ADDR_WIDTH1A: integer;
		ADDR_WIDTH1B: integer;
		DATA_WIDTH2A: integer;
		ADDR_WIDTH2A: integer;
		ADDR_WIDTH2B: integer;
		DATA_WIDTH3A: integer;
		ADDR_WIDTH3A: integer;
		ADDR_WIDTH3B: integer;
		DATA_WIDTH4A: integer;
		ADDR_WIDTH4A: integer;
		ADDR_WIDTH4B: integer
	);	
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		REG238 : IN std_logic_vector(7 downto 0);
		REG239 : IN std_logic_vector(7 downto 0);
		REG240 : IN std_logic_vector(7 downto 0);
		REG241 : IN std_logic_vector(7 downto 0);
		REG242 : IN std_logic_vector(7 downto 0);
		REG243 : IN std_logic_vector(7 downto 0);
		REG244 : IN std_logic_vector(7 downto 0);
		REG245 : IN std_logic_vector(7 downto 0);
		REG246 : IN std_logic_vector(7 downto 0);
		REG247 : IN std_logic_vector(7 downto 0);
		REG248 : IN std_logic_vector(7 downto 0);
		REG249 : IN std_logic_vector(7 downto 0);
		S1_1 : IN std_logic_vector(7 downto 0);
		S1_1_VALID : IN std_logic;
		S1_2 : IN std_logic_vector(7 downto 0);
		S1_2_VALID : IN std_logic;
		S1_3 : IN std_logic_vector(7 downto 0);
		S1_3_VALID : IN std_logic;
		S1_4 : IN std_logic_vector(7 downto 0);
		S1_4_VALID : IN std_logic;
		S2_1 : IN std_logic_vector(7 downto 0);
		S2_1_VALID : IN std_logic;
		S2_2 : IN std_logic_vector(7 downto 0);
		S2_2_VALID : IN std_logic;
		S2_3 : IN std_logic_vector(7 downto 0);
		S2_3_VALID : IN std_logic;
		S2_4 : IN std_logic_vector(7 downto 0);
		S2_4_VALID : IN std_logic;
		S3_1 : IN std_logic_vector(7 downto 0);
		S3_1_VALID : IN std_logic;
		S3_2 : IN std_logic_vector(7 downto 0);
		S3_2_VALID : IN std_logic;
		S3_3 : IN std_logic_vector(7 downto 0);
		S3_3_VALID : IN std_logic;
		S3_4 : IN std_logic_vector(7 downto 0);
		S3_4_VALID : IN std_logic;
		S4_1 : IN std_logic_vector(7 downto 0);
		S4_1_VALID : IN std_logic;
		S4_2 : IN std_logic_vector(7 downto 0);
		S4_2_VALID : IN std_logic;
		S4_3 : IN std_logic_vector(7 downto 0);
		S4_3_VALID : IN std_logic;
		S4_4 : IN std_logic_vector(7 downto 0);
		S4_4_VALID : IN std_logic;
		T16b_1 : IN std_logic_vector(15 downto 0);
		T16b_1_VALID : IN std_logic;
		T16b_2 : IN std_logic_vector(15 downto 0);
		T16b_2_VALID : IN std_logic;
		T16b_3 : IN std_logic_vector(15 downto 0);
		T16b_3_VALID : IN std_logic;
		T16b_4 : IN std_logic_vector(15 downto 0);
		T16b_4_VALID : IN std_logic;
		TRIGGER_REARM_TOGGLE : IN std_logic;
		FORCE_TRIGGER_TOGGLE : IN std_logic;
		SREG250_READ_TOGGLE : IN std_logic;
		START_CAPTURE_TOGGLE : IN std_logic;          
		SREG250 : OUT std_logic_vector(7 downto 0);
		SREG251 : OUT std_logic_vector(7 downto 0);
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;


	COMPONENT COMSCOPE
	generic (
		-- select features as needed: number of traces, widths
		-- One must re-synthesize after changing these choices.
		-- enable individual traces. '1' for enable, '0' for disable
		TRACE1_ENABLED: in std_logic;	
		TRACE2_ENABLED: in std_logic;	
		TRACE3_ENABLED: in std_logic;	
		TRACE4_ENABLED: in std_logic
	);	
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		SIGNED_REPRESENTATION_U_SIGNED_N : IN std_logic;
		REG237 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG238 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG239 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG240 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG241 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG242 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG243 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG244 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG245 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG246 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG247 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG248 : IN std_logic_vector(7 downto 0) := (others => '0');
		REG249 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_1_BIT_1_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_1_BIT_1_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_1_BIT_1_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_1_BIT_1_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_4 : IN std_logic;
--		SIGNAL_2_BIT_1_1 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_1_1 : IN std_logic;
--		SIGNAL_2_BIT_1_2 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_1_2 : IN std_logic;
--		SIGNAL_2_BIT_1_3 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_1_3 : IN std_logic;
--		SIGNAL_2_BIT_1_4 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_1_4 : IN std_logic;
--		SIGNAL_4_BIT_1_1 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_1_1 : IN std_logic;
--		SIGNAL_4_BIT_1_2 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_1_2 : IN std_logic;
--		SIGNAL_4_BIT_1_3 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_1_3 : IN std_logic;
--		SIGNAL_4_BIT_1_4 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_8_BIT_1_1 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_8_BIT_1_2 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_8_BIT_1_3 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_8_BIT_1_4 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_1_4 : IN std_logic;
--		SIGNAL_16_BIT_1_1 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_1_1 : IN std_logic;
--		SIGNAL_16_BIT_1_2 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_1_2 : IN std_logic;
--		SIGNAL_16_BIT_1_3 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_1_3 : IN std_logic;
--		SIGNAL_16_BIT_1_4 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_1_BIT_2_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_1_BIT_2_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_1_BIT_2_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_1_BIT_2_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_4 : IN std_logic;
--		SIGNAL_2_BIT_2_1 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_2_1 : IN std_logic;
--		SIGNAL_2_BIT_2_2 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_2_2 : IN std_logic;
--		SIGNAL_2_BIT_2_3 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_2_3 : IN std_logic;
--		SIGNAL_2_BIT_2_4 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_2_4 : IN std_logic;
--		SIGNAL_4_BIT_2_1 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_2_1 : IN std_logic;
--		SIGNAL_4_BIT_2_2 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_2_2 : IN std_logic;
--		SIGNAL_4_BIT_2_3 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_2_3 : IN std_logic;
--		SIGNAL_4_BIT_2_4 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_8_BIT_2_1 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_8_BIT_2_2 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_8_BIT_2_3 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_8_BIT_2_4 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_2_4 : IN std_logic;
--		SIGNAL_16_BIT_2_1 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_2_1 : IN std_logic;
--		SIGNAL_16_BIT_2_2 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_2_2 : IN std_logic;
--		SIGNAL_16_BIT_2_3 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_2_3 : IN std_logic;
--		SIGNAL_16_BIT_2_4 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_1_BIT_3_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_1_BIT_3_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_1_BIT_3_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_1_BIT_3_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_4 : IN std_logic;
--		SIGNAL_2_BIT_3_1 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_3_1 : IN std_logic;
--		SIGNAL_2_BIT_3_2 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_3_2 : IN std_logic;
--		SIGNAL_2_BIT_3_3 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_3_3 : IN std_logic;
--		SIGNAL_2_BIT_3_4 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_3_4 : IN std_logic;
--		SIGNAL_4_BIT_3_1 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_3_1 : IN std_logic;
--		SIGNAL_4_BIT_3_2 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_3_2 : IN std_logic;
--		SIGNAL_4_BIT_3_3 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_3_3 : IN std_logic;
--		SIGNAL_4_BIT_3_4 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_8_BIT_3_1 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_8_BIT_3_2 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_8_BIT_3_3 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_8_BIT_3_4 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_3_4 : IN std_logic;
--		SIGNAL_16_BIT_3_1 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_3_1 : IN std_logic;
--		SIGNAL_16_BIT_3_2 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_3_2 : IN std_logic;
--		SIGNAL_16_BIT_3_3 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_3_3 : IN std_logic;
--		SIGNAL_16_BIT_3_4 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_1_BIT_4_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_1_BIT_4_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_1_BIT_4_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_1_BIT_4_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_4 : IN std_logic;
--		SIGNAL_2_BIT_4_1 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_4_1 : IN std_logic;
--		SIGNAL_2_BIT_4_2 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_4_2 : IN std_logic;
--		SIGNAL_2_BIT_4_3 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_4_3 : IN std_logic;
--		SIGNAL_2_BIT_4_4 : IN std_logic_vector(1 downto 0) := (others => '0');
--		SIGNAL_2_BIT_SAMPLE_CLK_4_4 : IN std_logic;
--		SIGNAL_4_BIT_4_1 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_4_1 : IN std_logic;
--		SIGNAL_4_BIT_4_2 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_4_2 : IN std_logic;
--		SIGNAL_4_BIT_4_3 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_4_3 : IN std_logic;
--		SIGNAL_4_BIT_4_4 : IN std_logic_vector(3 downto 0) := (others => '0');
--		SIGNAL_4_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		SIGNAL_8_BIT_4_1 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_8_BIT_4_2 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_8_BIT_4_3 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_8_BIT_4_4 : IN std_logic_vector(7 downto 0) := (others => '0');
		SIGNAL_8_BIT_SAMPLE_CLK_4_4 : IN std_logic;
--		SIGNAL_16_BIT_4_1 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_4_1 : IN std_logic;
--		SIGNAL_16_BIT_4_2 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_4_2 : IN std_logic;
--		SIGNAL_16_BIT_4_3 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_4_3 : IN std_logic;
--		SIGNAL_16_BIT_4_4 : IN std_logic_vector(15 downto 0) := (others => '0');
--		SIGNAL_16_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		TRIGGER_1_BIT_1 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_1_BIT_2 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_1_BIT_3 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_1_BIT_4 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_4 : IN std_logic;
--		TRIGGER_2_BIT_1 : IN std_logic_vector(1 downto 0) := (others => '0');
--		TRIGGER_2_BIT_SAMPLE_CLK_1 : IN std_logic;
--		TRIGGER_2_BIT_2 : IN std_logic_vector(1 downto 0) := (others => '0');
--		TRIGGER_2_BIT_SAMPLE_CLK_2 : IN std_logic;
--		TRIGGER_2_BIT_3 : IN std_logic_vector(1 downto 0) := (others => '0');
--		TRIGGER_2_BIT_SAMPLE_CLK_3 : IN std_logic;
--		TRIGGER_2_BIT_4 : IN std_logic_vector(1 downto 0) := (others => '0');
--		TRIGGER_2_BIT_SAMPLE_CLK_4 : IN std_logic;
--		TRIGGER_4_BIT_1 : IN std_logic_vector(3 downto 0) := (others => '0');
--		TRIGGER_4_BIT_SAMPLE_CLK_1 : IN std_logic;
--		TRIGGER_4_BIT_2 : IN std_logic_vector(3 downto 0) := (others => '0');
--		TRIGGER_4_BIT_SAMPLE_CLK_2 : IN std_logic;
--		TRIGGER_4_BIT_3 : IN std_logic_vector(3 downto 0) := (others => '0');
--		TRIGGER_4_BIT_SAMPLE_CLK_3 : IN std_logic;
--		TRIGGER_4_BIT_4 : IN std_logic_vector(3 downto 0) := (others => '0');
--		TRIGGER_4_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_8_BIT_1 : IN std_logic_vector(7 downto 0) := (others => '0');
		TRIGGER_8_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_8_BIT_2 : IN std_logic_vector(7 downto 0) := (others => '0');
		TRIGGER_8_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_8_BIT_3 : IN std_logic_vector(7 downto 0) := (others => '0');
		TRIGGER_8_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_8_BIT_4 : IN std_logic_vector(7 downto 0) := (others => '0');
		TRIGGER_8_BIT_SAMPLE_CLK_4 : IN std_logic;
--		TRIGGER_16_BIT_1 : IN std_logic_vector(15 downto 0) := (others => '0');
--		TRIGGER_16_BIT_SAMPLE_CLK_1 : IN std_logic;
--		TRIGGER_16_BIT_2 : IN std_logic_vector(15 downto 0) := (others => '0');
--		TRIGGER_16_BIT_SAMPLE_CLK_2 : IN std_logic;
--		TRIGGER_16_BIT_3 : IN std_logic_vector(15 downto 0) := (others => '0');
--		TRIGGER_16_BIT_SAMPLE_CLK_3 : IN std_logic;
--		TRIGGER_16_BIT_4 : IN std_logic_vector(15 downto 0) := (others => '0');
--		TRIGGER_16_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_REARM_TOGGLE : IN std_logic;
		FORCE_TRIGGER_TOGGLE : IN std_logic;
		SREG250_READ_TOGGLE : IN std_logic;
		START_CAPTURE_TOGGLE : IN std_logic;          
		REG250 : OUT std_logic_vector(7 downto 0) := (others => '0');
		REG251 : OUT std_logic_vector(7 downto 0) := (others => '0');
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;

--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
-- Suffix _D indicates a one CLK delayed version of the net with the same name
-- Suffix _X indicates an extended precision version of the net with the same name
-- Suffix _N indicates an inverted version of the net with the same name


--// CLOCKS, RESETS
signal CLKREF_TCXOg: std_logic := '0';
signal CLKREF25Bg: std_logic := '0';
signal CLKREF25Cg: std_logic := '0';
signal PLL25_CLKFB: std_logic := '0';
signal PLL25_LOCKED: std_logic := '0';
signal CLKGEN7C_INPUT_CLK_STOPPED: std_logic := '0';
signal CLKGEN7C_LOCKED: std_logic := '0';
signal CLKGEN7D_INPUT_CLK_STOPPED: std_logic := '0';
signal CLKGEN7D_LOCKED: std_logic := '0';
signal CLK125: std_logic := '0';
signal CLKREF_OUT_B: std_logic := '0';
signal CLK10: std_logic := '0';
signal CLK10g: std_logic := '0';
signal CLKREF_EXTg: std_logic := '0';
constant CLK_FREQUENCY: integer := 125; -- processing clock frequency CLK_P in MHz, as time reference
signal TICK_100MS: std_logic := '0';
signal TICK_1S: std_logic := '0';
signal TICK_4US: std_logic := '0';
signal TICK_100MS_CNTR: unsigned(3 downto 0) := (others => '0');
signal RESET_COUNTER: unsigned(23 downto 0) := x"000000";	-- initialize for simulations
	-- spans 2^23/10MHz = 838ms
signal RESET_STATE: integer range 0 to 1 := 0;
signal ASYNC_RESET: std_logic := '1';
signal ASYNC_RESET_D: std_logic := '1';
signal ASYNC_RESET_D2: std_logic := '1';
signal CLK_P: std_logic := '0';
signal SYNC_RESET_CLK_P: std_logic := '0';
signal READY_FLAG_CLK_P: std_logic := '0';

--//-- ETHERNET MAC#1-----------------------------------
signal CLK_SKEW11: std_logic_vector(15 downto 0) := (others => '0');
signal CLK_SKEW12: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_MAC_ADDR: std_logic_vector(47 downto 0) := (others => '0');
signal LAN1_TP: std_logic_vector(10 downto 1) := (others => '0');
signal LAN1_PHY_ID: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_MAC_RX_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal LAN1_MAC_RX_DATA_VALID: std_logic:= '0';
signal LAN1_MAC_RX_SOF: std_logic:= '0';
signal LAN1_MAC_RX_EOF: std_logic:= '0';
signal LAN1_MAC_TX_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal LAN1_MAC_TX_DATA_VALID: std_logic:= '0';
signal LAN1_MAC_TX_EOF: std_logic:= '0';
signal LAN1_MAC_TX_CTS: std_logic:= '0';
signal LAN1_LINK_STATUS: std_logic:= '0';
signal LAN1_SPEED_STATUS: std_logic_vector(1 downto 0) := (others => '0');
signal LAN1_DUPLEX_STATUS: std_logic:= '0';
signal LAN1_N_RX_BAD_CRCS:  std_logic_vector(15 downto 0);

--//-- IP STACK #1  -----------------------------------
constant NTCPSTREAMS2: integer := 2;  -- number of concurrent TCP streams handled by this component
signal IP2_ADDRv4: std_logic_vector(31 downto 0) := (others => '0');	
signal SUBNET_MASK: std_logic_vector(31 downto 0) := (others => '0');	
signal GATEWAY_IP_ADDR: std_logic_vector(31 downto 0) := (others => '0');	
signal MULTICAST_IP_ADDR: std_logic_vector(31 downto 0) := (others => '0');	
signal IPSTACK2_TP: std_logic_vector(10 downto 1) := (others => '0');
signal LAN1_UDP_TX_DATA1: std_logic_vector(7 downto 0) := (others => '0');
signal LAN1_UDP_TX_DATA2: std_logic_vector(7 downto 0) := (others => '0');
signal LAN1_UDP_TX_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal LAN1_UDP_TX_DATA1_VALID: std_logic := '0';
signal LAN1_UDP_TX_DATA2_VALID: std_logic := '0';
signal LAN1_UDP_TX_DATA_VALID: std_logic := '0';
signal LAN1_UDP_TX_SOF: std_logic := '0';
signal LAN1_UDP_TX_EOF: std_logic := '0';
signal LAN1_UDP_TX_CTS: std_logic := '0';
signal LAN1_UDP_TX_ACK: std_logic := '0';
signal LAN1_UDP_TX_NAK: std_logic := '0';
signal LAN1_UDP_TX_DEST_IP_ADDR: std_logic_vector(127 downto 0) := (others => '0');
signal LAN1_UDP_TX_DEST_PORT_NO: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_UDP_TX_DEST_PORT_NO1: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_TCP_RX_DATA: SLV8xNTCPSTREAMStype;
signal LAN1_TCP_RX_DATA_VALID: std_logic_vector((NTCPSTREAMS2-1) downto 0) := (others => '0');
signal LAN1_TCP_RX_CTS: std_logic_vector((NTCPSTREAMS2-1) downto 0) := (others => '0');
signal LAN1_TCP_TX_DATA: SLV8xNTCPSTREAMStype;
signal LAN1_TCP_TX_DATA_VALID: std_logic_vector((NTCPSTREAMS2-1) downto 0) := (others => '0');
signal LAN1_TCP_TX_CTS: std_logic_vector((NTCPSTREAMS2-1) downto 0) := (others => '0');
signal LAN1_RX_DATA1_X: std_logic_vector(8 downto 0) := (others => '0');
signal LAN1_RX_SAMPLE1_CLK: std_logic := '0';

--// LAN/TCP-IP Interface for M&C (port 1028)
signal RX_LAN: std_logic_vector(7 downto 0) := (others => '0'); 
signal RX_LAN_SAMPLE_CLK_REQ: std_logic;
signal RX_LAN_BUFFER_EMPTY: std_logic := '1';
signal RX_LAN_BUFFER_EMPTY_D: std_logic := '1';
signal RX_LAN_BUFFER_EMPTY_D2: std_logic := '1';
signal TX_LAN_TOGGLE: std_logic;
signal TX_LAN_TOGGLE_D: std_logic;
signal TX_LAN_TOGGLE_D2: std_logic;

--//-- DDR3 SODIMM CONTROLLER  -----------------------------------------------
-- optional
constant DDR3_ENABLED : std_logic := '1';    -- 0/1 to instantiate DDR3 SDRAM memory controller
signal DDR3_STARTADDR : std_logic_vector(31 downto 0) := (others => '0');
signal DDR3_CEILINGADDR : std_logic_vector(31 downto 0) := (others => '0');
signal DDR3_PLL_LOCKED_OUT: std_logic := '0';
signal DDR3_TP : std_logic_vector(20 downto 1) := (others => '0');
signal DDR3_DATA1_IN : std_logic_vector(511 downto 0) := (others => '0');
signal DDR3_DATA1_IN_VALID : std_logic := '0';
signal DDR3_DATA1_IN_CTS : std_logic := '0';
signal DDR3_DATA1_IN_SETADDR : std_logic := '0';
signal DDR3_DATA1_IN_STARTADDR : std_logic_vector(31 downto 0) := (others => '0');
signal DDR3_DATA1_IN_CEILINGADDR : std_logic_vector(31 downto 0) := (others => '0');
signal DDR3_DATA1_IN_MODE : std_logic_vector(1 downto 0) := (others => '0');
signal DDR3_WRITE_COMMAND_COMPLETE: std_logic := '1';
signal DDR3_WR_ADDR : unsigned(31 downto 0) := (others => '0');
signal DDR3_WR_ADDR_PLUS8 : unsigned(31 downto 0) := (others => '0');

signal DDR3_DATA1_OUT : std_logic_vector(511 downto 0) := (others => '0');
signal DDR3_DATA1_OUT_VALID : std_logic := '0';
signal DDR3_DATA1_OUT_CTS : std_logic := '0';
signal DDR3_DATA1_OUT_EMPTY : std_logic := '0';
signal DDR3_DATA1_OUT_SETADDR : std_logic := '0';
signal DDR3_DATA1_OUT_STARTADDR : std_logic_vector(31 downto 0) := (others => '0');
signal DDR3_DATA1_OUT_CEILINGADDR : std_logic_vector(31 downto 0) := (others => '0');
signal DDR3_DATA1_OUT_MODE : std_logic_vector(1 downto 0) := (others => '0');
signal DDR3_RD_ADDR : unsigned(31 downto 0) := (others => '0');
signal DDR3_RD_ADDR_PLUS8 : unsigned(31 downto 0) := (others => '0');
signal FIRST_READ_WORD_FLAG: std_logic := '0';

signal DDR3_MEMORY_RDY_OUT : std_logic := '0';
signal DDR3_DATA1_IN_ADDR : std_logic_vector(31 downto 0) := (others => '0');
signal DDR3_DATA1_OUT_ADDR : std_logic_vector(31 downto 0) := (others => '0');
-- test test test
signal DDR3_TEST_STATE: integer range 0 to 6 := 0;

--// COM-30xx RF RECEIVER  -----------------------------------------------
-- optional RF receiver connected through the right (J8) connector
-- Mutually exclusive with COM2802_ENABLED below
constant COM30XX_J8_ENABLED: std_logic := '1';    -- 0/1 to disable/enable
signal clkfbout: std_logic := '0';
signal CLK99: std_logic := '0';

--// COM-2802 QUAD DDS DRIVER  -----------------------------------------------
-- optional quad DDS synthesizers through the right (J8) connector
-- Mutually exclusive with COM30XX_J8_ENABLED below
constant COM2802_ENABLED : std_logic := '0';    -- 0/1 to disable/enable
signal DDSA_CLK_IN: std_logic := '0';
signal DDSB_CLK_IN: std_logic := '0';
signal DDSC_CLK_IN: std_logic := '0';
signal DDSD_CLK_IN: std_logic := '0';
signal TR1: unsigned(15 downto 0) := (others => '0');
signal TR2: unsigned(15 downto 0) := (others => '0');
signal COM2802A_DOUT: std_logic_vector(15 downto 0) := (others => '0');
signal COM2802B_DOUT: std_logic_vector(15 downto 0) := (others => '0');
signal COM2802C_DOUT: std_logic_vector(15 downto 0) := (others => '0');
signal COM2802D_DOUT: std_logic_vector(15 downto 0) := (others => '0');
signal COM2802A_TX_ENABLE_OUT: std_logic := '0';
signal COM2802B_TX_ENABLE_OUT: std_logic := '0';
signal COM2802C_TX_ENABLE_OUT: std_logic := '0';
signal COM2802D_TX_ENABLE_OUT: std_logic := '0';

--// Interface for M&C
signal SREG254_READ_TOGGLE_D: std_logic := '0';
signal SREG254_READ_TOGGLE_D2: std_logic := '0';

--// ComScope traces
signal S1_1: std_logic_vector(7 downto 0) := (others => '0');	
signal S1_1_CLK: std_logic := '0';
signal S1_2: std_logic_vector(7 downto 0) := (others => '0');	
signal S1_2_CLK: std_logic := '0';
signal S1_2B_CLK: std_logic := '0';
signal S1_3: std_logic_vector(7 downto 0) := (others => '0');	
signal S1_3_CLK: std_logic := '0';
signal S1_3B_CLK: std_logic := '0';
signal S1_4: std_logic_vector(7 downto 0) := (others => '0');	
signal S1_4_CLK: std_logic := '0';
signal S1_4B_CLK: std_logic := '0';
signal S2_1: std_logic_vector(7 downto 0) := (others => '0');	
signal S2_1_CLK: std_logic := '0';
signal S2_1B_CLK: std_logic := '0';
signal S2_2: std_logic_vector(7 downto 0) := (others => '0');	
signal S2_2_CLK: std_logic := '0';
signal S2_2B_CLK: std_logic := '0';
signal S2_3: std_logic_vector(7 downto 0) := (others => '0');	
signal S2_3_CLK: std_logic := '0';
signal S2_3B_CLK: std_logic := '0';
signal S2_4: std_logic_vector(7 downto 0) := (others => '0');	
signal S2_4_CLK: std_logic := '0';
signal S2_4B_CLK: std_logic := '0';
signal S3_1: std_logic_vector(7 downto 0) := (others => '0');	
signal S3_1_CLK: std_logic := '0';
signal S3_1B_CLK: std_logic := '0';
signal S3_2: std_logic_vector(7 downto 0) := (others => '0');	
signal S3_2_CLK: std_logic := '0';
signal S3_2B_CLK: std_logic := '0';
signal S3_3: std_logic_vector(7 downto 0) := (others => '0');	
signal S3_3_CLK: std_logic := '0';
signal S3_3B_CLK: std_logic := '0';
signal S3_4: std_logic_vector(7 downto 0) := (others => '0');	
signal S3_4_CLK: std_logic := '0';
signal S3_4B_CLK: std_logic := '0';
signal S4_1: std_logic_vector(7 downto 0) := (others => '0');	
signal S4_1_CLK: std_logic := '0';
signal S4_1B_CLK: std_logic := '0';
signal S4_2: std_logic_vector(7 downto 0) := (others => '0');	
signal S4_2_CLK: std_logic := '0';
signal S4_2B_CLK: std_logic := '0';
signal S4_3: std_logic_vector(7 downto 0) := (others => '0');	
signal S4_3_CLK: std_logic := '0';
signal S4_3B_CLK: std_logic := '0';
signal S4_4: std_logic_vector(7 downto 0) := (others => '0');	
signal S4_4_CLK: std_logic := '0';
signal S4_4B_CLK: std_logic := '0';

signal T1: std_logic := '0';
signal T1_CLK: std_logic := '0';
signal T2: std_logic := '0';
signal T2_CLK: std_logic := '0';

signal TRIGGER_REARM_TOGGLE: std_logic:= '0';
signal FORCE_TRIGGER_TOGGLE: std_logic:= '0';
signal START_CAPTURE_TOGGLE: std_logic:= '0';
signal SREG250_READ_TOGGLE: std_logic := '0';
signal COMSCOPE2_TP: std_logic_vector(10 downto 1) := (others => '0');	

--//-- DNA Port ------------------------------------
signal DNA_ID_DATA: std_logic_vector(56 downto 0) := (others => '0');
signal DNA_ID_SAMPLE_CLK: std_logic := '0';

--// ARM co-processor interface
signal UC_WEBG: std_logic := '0';  -- WE# through global buffer
signal UC_REBG: std_logic := '0';	-- RE# through global buffer
signal UC_ADDRESS: unsigned(7 downto 0) := (others => '0');
signal UC_AD_LOCAL: std_logic_vector(7 downto 0) := (others => '0');
signal UC_RDN_D: std_logic := '0';
signal UC_RDN_D2: std_logic := '0';
signal CONFIG_CHANGE_TOGGLE: std_logic := '0';
signal CONFIG_CHANGE_TOGGLE_D: std_logic := '0';
signal CONFIG_CHANGE_TOGGLE_D2: std_logic := '0';
signal CONFIG_CHANGE_PULSE: std_logic := '0';

--// Control Registers
constant NCREGS: integer := 100;	-- number of control registers.
constant NCREG_IMIN: integer := 0;	-- starting at this index
constant NCREG_IMAX: integer := (NCREG_IMIN+NCREGS-1);
type SLV8xNCREGStype is array (integer range NCREG_IMIN to NCREG_IMAX) of std_logic_vector(7 downto 0);
signal CREG: SLV8xNCREGStype := (others => (others => '0'));
signal REG255: std_logic_vector(7 downto 0) := (others => '0');

--// User-defined status Registers (add as needed)
constant NSREGS: integer := 39;	-- number of status registers.
constant NSREG_IMIN: integer := 7;	-- starting at this index
constant NSREG_IMAX: integer := (NSREG_IMIN+NSREGS-1);
type SLV8xNSREGStype is array (integer range NSREG_IMIN to NSREG_IMAX) of std_logic_vector(7 downto 0);
signal SREG: SLV8xNSREGStype := (others => (others => '0'));
signal SREG7_READ_TOGGLE: std_logic := '0';
signal SREG7_READ_TOGGLE_D: std_logic := '0';
signal SREG7_READ_TOGGLE_D2: std_logic := '0';
signal LATCH_MONITORING_PULSE: std_logic := '0';
signal SREG254_READ_TOGGLE: std_logic := '0';			

--// ComScope control registers
signal REG237: std_logic_vector(7 downto 0):= "00000000";
signal REG238: std_logic_vector(7 downto 0):= "00000000";
signal REG239: std_logic_vector(7 downto 0):= "00000000";
signal REG240: std_logic_vector(7 downto 0):= "00001101";	-- Trace 1 signal selection
signal REG241: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG242: std_logic_vector(7 downto 0):= "00001110";	-- Trace 2 signal selection
signal REG243: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG244: std_logic_vector(7 downto 0):= "00000000";	-- Trace 3 signal selection
signal REG245: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG246: std_logic_vector(7 downto 0):= "00000000";	-- Trace 4 signal selection
signal REG247: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG248: std_logic_vector(7 downto 0):= "10001101";	-- Trigger edge, trigger signal
signal REG249: std_logic_vector(7 downto 0):= "10111111";	-- Trigger threshold
signal REG250: std_logic_vector(7 downto 0):= "00000000";
signal REG251: std_logic_vector(7 downto 0):= "00000000";



signal TESTS11: signed(7 downto 0) := (others => '0');
--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
begin
--// CLOCKS, RESET ---------------------
-- if OPTION = 'A' (ASCII 0x41), frequency reference is 19.2 MHz VCTCXO on the board.
-- Frequency plan: 19.2 MHz -> 10 MHz -> 125 MHz processing clock
-- if OPTION = 'B' (ASCII 0x42), frequency reference is external 10 MHz VCTCXO on the board. Must be present at power up otherwise nothing will work.
-- Frequency plan: 10 MHz -> 125 MHz processing clock

CLK10_GEN: if(SIMULATION = '1') generate
	 -- 10 MHz
    process
    begin
        CLK10g <= '0';
        wait for 50 ns;
        CLK10g <= '1';
        wait for 50 ns;
    end process;
	 CLKGEN7C_LOCKED <= '1';
	 CLKGEN7C_INPUT_CLK_STOPPED <= '0';

    -- 19.2 MHz
    process
    begin
        CLKREF_TCXOg <= '0';
        wait for 26.04 ns;
        CLKREF_TCXOg <= '1';
        wait for 26.04 ns;
    end process;

	 -- 25 MHz 
    process
    begin
        CLKREF25Bg <= '0';
        wait for 20.0 ns;
        CLKREF25Bg <= '1';
        wait for 20.0 ns;
    end process;
	 
end generate;

-- regenerate the 25 MHz clock
  plle2_adv_inst : PLLE2_ADV
generic map
 (BANDWIDTH            => "LOW",

  
  COMPENSATION         => "ZHOLD",
  DIVCLK_DIVIDE        => 1,
  CLKFBOUT_MULT        => 32,
  CLKFBOUT_PHASE       => 0.000,
  CLKOUT0_DIVIDE       => 32,
  CLKOUT0_PHASE        => 0.000,
  CLKOUT0_DUTY_CYCLE   => 0.500,
  CLKIN1_PERIOD        => 40.0)
port map
  -- Output clocks
 (
  CLKFBOUT            => PLL25_CLKFB,
  CLKOUT0             => CLKREF25Cg,
  CLKOUT1             => open,
  CLKOUT2             => open,
  CLKOUT3             => open,
  CLKOUT4             => open,
  CLKOUT5             => open,
  -- Input clock control
  CLKFBIN             => PLL25_CLKFB,
  CLKIN1              => CLKREF25Bg,
  CLKIN2              => '0',
  -- Tied to always select the primary input clock
  CLKINSEL            => '1',
  -- Ports for dynamic reconfiguration
  DADDR               => (others => '0'),
  DCLK                => '0',
  DEN                 => '0',
  DI                  => (others => '0'),
  DO                  => open,
  DRDY                => open,
  DWE                 => '0',
  -- Other control and status signals
  LOCKED              => PLL25_LOCKED,
  PWRDWN              => '0',
  RST                 => not RESET_COUNTER(17));


-- generate 10 MHz from 19.2 MHz VCTCXO + BUFG 25 MHz crystal oscillator
INTERNAL_FREQ_REF: if(OPTION = x"41") and (SIMULATION = '0') generate
	BUFG_001: BUFG port map(I => CLKREF_TCXO, O=> CLKREF_TCXOg);
	BUFG_002: BUFG port map(I => CLKREF25B, O=> CLKREF25Bg);
	BUFG_003: BUFG port map (I => CLK10, O => CLK10g);

	CLKGEN7C: CLKGEN7_MMCM_ADJ 
	GENERIC MAP(
		CLKFBOUT_MULT_F => 50.000,
        CLKOUT0_DIVIDE_F => 96.000,
        CLKIN1_PERIOD => 52.083
    ) 
    PORT MAP(
        CLK_IN1 => CLKREF_TCXOg,	-- 19.2 MHz TCXO clock 
        CLK_OUT1 => CLK10,	-- 10 MHz not global
        INPUT_CLK_STOPPED => CLKGEN7C_INPUT_CLK_STOPPED,
        LOCKED => CLKGEN7C_LOCKED
    );
end generate;

-- OR use external 10 MHz frequency reference
EXTERNAL_FREQ_REF: if(OPTION = x"42") and (SIMULATION = '0') generate
	BUFG_002: BUFG port map(I => CLKREF25B, O=> CLKREF25Bg);
	BUFG_003: BUFG port map (I => CLKREF_EXT, O => CLK10g);
end generate;

-- generate 125 MHz processing clock from 10 MHz reference
CLKGEN7D: CLKGEN7_MMCM_ADJ 
GENERIC MAP(
	CLKFBOUT_MULT_F => 62.500,
	CLKOUT0_DIVIDE_F => 5.000,
	CLKIN1_PERIOD => 100.000
 ) 
PORT MAP(
	CLK_IN1 => CLK10g,	-- 10 MHz 
	CLK_OUT1 => CLK125,	-- 125 MHz not global
	INPUT_CLK_STOPPED => CLKGEN7D_INPUT_CLK_STOPPED,
	LOCKED => CLKGEN7D_LOCKED
);
BUFG_002: BUFG port map(I => CLK125, O => CLK_P);

SREG(9)(2 downto 0) <= DDR3_PLL_LOCKED_OUT & CLKGEN7D_LOCKED & CLKGEN7C_LOCKED;

RESET_STATE_MACHINE_001A: if(OPTION = x"41") generate
    -- Generate miscellaneous global clocks and resets from the 
    -- reference 19.2 MHz clock (VCTCXO)
    RESET_STATE_MACHINE_001: process(CLKREF_TCXOg)
    begin
        if rising_edge(CLKREF_TCXOG) then
            -- PLL need time to lock. The reset of the application is still in reset
            if(RESET_COUNTER(17) = '0') and (SIMULATION = '0') then
                -- wait a bit before asserting the PLL lock
                RESET_COUNTER <= RESET_COUNTER + 1;
            elsif(RESET_COUNTER(5) = '0') and (SIMULATION = '1') then  
                -- make it short during simulations
                -- wait a bit before asserting the PLL lock
                RESET_COUNTER <= RESET_COUNTER + 1;
            elsif(CLKGEN7C_LOCKED = '1') and (CLKGEN7D_LOCKED = '1') 
				and ((DDR3_ENABLED = '0') or (DDR3_PLL_LOCKED_OUT = '1')) then
                -- wait until all used PLLs are locked
                RESET_STATE <= 1;
            end if;
            
            if(RESET_STATE = 1) then
                ASYNC_RESET <= '0';
            else
                ASYNC_RESET <= '1';
            end if;
        end if;
    end process;
end generate;

RESET_STATE_MACHINE_001B: if(OPTION = x"42") generate
    -- Generate miscellaneous global clocks and resets from the 
    -- external reference 10 MHz clock 
    RESET_STATE_MACHINE_001: process(CLK10g)
    begin
        if rising_edge(CLK10g) then
            -- PLL need time to lock. The reset of the application is still in reset
            if(RESET_COUNTER(17) = '0') and (SIMULATION = '0') then
                -- wait a bit before asserting the PLL lock
                RESET_COUNTER <= RESET_COUNTER + 1;
            elsif(RESET_COUNTER(5) = '0') and (SIMULATION = '1') then  
                -- make it short during simulations
                -- wait a bit before asserting the PLL lock
                RESET_COUNTER <= RESET_COUNTER + 1;
            elsif(CLKGEN7D_LOCKED = '1') and ((DDR3_ENABLED = '0') or (DDR3_PLL_LOCKED_OUT = '1')) then
                -- assert the PLL lock
                RESET_STATE <= 1;
            end if;
            
            if(RESET_STATE = 1) then
                ASYNC_RESET <= '0';
            else
                ASYNC_RESET <= '1';
            end if;
        end if;
    end process;
end generate;


-- generate a reset synchronous with CLK_P at the end of the ASYNC_RESET
SYNC_RESET_CLK_P_GEN: process(ASYNC_RESET, CLK_P)
begin
	if rising_edge(CLK_P) then
		ASYNC_RESET_D <= ASYNC_RESET;
		ASYNC_RESET_D2 <= ASYNC_RESET_D;
		
		if(ASYNC_RESET_D = '0') and (ASYNC_RESET_D2 = '1')  then
			SYNC_RESET_CLK_P <= '1';
		else
			SYNC_RESET_CLK_P <= '0';
		end if;
		
		-- '0' from power-up/async_reset until FPGA is ready
		if(SYNC_RESET_CLK_P = '1') then
			READY_FLAG_CLK_P <= '1';
		end if;
	end if;
end process;

	-- external input clock
BUFG_006: BUFG  port map (I=> UC_WEB_IN, O=> UC_WEBG);	
	-- ARM WE#
BUFG_007: BUFG  port map (I=> UC_REB_IN, O=> UC_REBG);	
	-- ARM RE#

-- 1s tick
TICK1S_001: TIMER_4US 
GENERIC MAP(
	CLK_FREQUENCY => CLK_FREQUENCY
)
PORT MAP(
	ASYNC_RESET => SYNC_RESET_CLK_P,
	CLK => CLK_P,
	TICK_4US => TICK_4US,
	TICK_100MS => TICK_100MS
);
	
-- modulo-10 counter. 1s tick
TICK1S_002: process(CLK_P)
begin
	if rising_edge(CLK_P) then
		if(SYNC_RESET_CLK_P = '1') then
			TICK_100MS_CNTR <= "0000";
			TICK_1S <= '0';
		elsif(TICK_100MS = '1') then
			if(TICK_100MS_CNTR = 0) then
				TICK_100MS_CNTR <= "1001";
				TICK_1S <= '1';
			else
				TICK_100MS_CNTR <= TICK_100MS_CNTR - 1;
				TICK_1S <= '0';
			end if;
		else
			TICK_1S <= '0';
		end if;
	end if;
end process;

--//-- ETHERNET MAC#1  -----------------------------------
-- Interface with board GbE PHY: Micrel KSZ9031
CLK_SKEW11 <= x"0310"; 	 --(INTERNAL_PHY_CLKS_DELAYS => '0')
CLK_SKEW12 <= x"0000";    -- future	

-- new: MAC address automatically generated from unique DNA_ID
LAN1_MAC_ADDR_GEN: process(CLK_P)
begin
	if rising_edge(CLK_P) then
		if(DNA_ID_SAMPLE_CLK = '1') then
				LAN1_MAC_ADDR <= x"00" & DNA_ID_DATA(39 downto 1) & "1";	-- unique, unicast
		end if;
	end if;
end process;

LAN_001: COM5401 
GENERIC MAP(
	MII_SEL => '0',   	   -- select which MII interface: 0 = RGMII, 1 = GMII/MII
	PHY_ADDR => "00111",   -- PHY_AD0/1 pulled-up, PHY_AD2 pulled-up in .ucf file.
	CLK_FREQUENCY => CLK_FREQUENCY,
	PLATFORM => 7,	       -- 7 series Xilinx FPGA
	TARGET_PHY => 3,       -- target PHY: KSZ9031
	INTERNAL_PHY_CLKS_DELAYS => '0',
	SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK_P,
	SYNC_RESET => not READY_FLAG_CLK_P,	-- new 12/9/15 more reliable start
	MAC_TX_CONFIG => X"0003",	-- MAC must must provide pad + crc32
	MAC_RX_CONFIG => x"000F",	-- promiscuous mode, strip crc32, accept broadcast/multicast
	MAC_ADDR => LAN1_MAC_ADDR,
	PHY_CONFIG_CHANGE => CONFIG_CHANGE_PULSE,	
	PHY_RESET => '0',
	SPEED => "11",	-- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	DUPLEX => '1',	-- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	TEST_MODE => "00",	-- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	POWER_DOWN => '0', -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	CLK_SKEW1 => CLK_SKEW11, -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	CLK_SKEW2 => CLK_SKEW12, -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	MAC_TX_DATA => LAN1_MAC_TX_DATA,
	MAC_TX_DATA_VALID => LAN1_MAC_TX_DATA_VALID,
	MAC_TX_EOF => LAN1_MAC_TX_EOF,
	MAC_TX_CTS => LAN1_MAC_TX_CTS,
	MAC_RX_DATA => LAN1_MAC_RX_DATA,	
	MAC_RX_DATA_VALID => LAN1_MAC_RX_DATA_VALID,
	MAC_RX_SOF => LAN1_MAC_RX_SOF,
	MAC_RX_EOF => LAN1_MAC_RX_EOF,
	MAC_RX_CTS => '1',  -- follow-on processing is expected to always accept data even at max speed.
	-- RGMII interface ----------------
	TXC => LAN_TXC,	
	TXD => LAN_TXD,
	TX_CTL => LAN_TX_CTL,
	RXC => LAN_RXC,
	RXD => LAN_RXD,
	RX_CTL => LAN_RX_CTL,
	RESET_N => LAN_RESET_N,
	MCLK => LAN_MCLK,
	MDIO => LAN_MDIO,	
	-- end of RGMII interface --------
	MII_TX_CLK => '0',	-- MII interface is unused -----
	GMII_TX_CLK => open,
	GMII_MII_TXD => open,
	GMII_MII_TX_EN => open,
	GMII_MII_TX_ER => open,
	GMII_MII_CRS => '0',
	GMII_MII_COL => '0',
	GMII_MII_RX_CLK => '0',
	GMII_MII_RXD => x"00",
	GMII_MII_RX_DV => '0',
	GMII_MII_RX_ER => '0',  -- end of MII interface ------
	LINK_STATUS => LAN1_LINK_STATUS,
	SPEED_STATUS => LAN1_SPEED_STATUS,
	DUPLEX_STATUS => LAN1_DUPLEX_STATUS,
	PHY_ID => LAN1_PHY_ID,
	N_RX_FRAMES => open,
	N_RX_BAD_CRCS => LAN1_N_RX_BAD_CRCS,
	N_RX_FRAMES_TOO_SHORT => open,
	N_RX_FRAMES_TOO_LONG => open,
	N_RX_WRONG_ADDR => open,
	N_RX_LENGTH_ERRORS => open,
	CS_CLKG => open,
	CS1 => open,
	CS1_CLK => open,
	CS2 => open,
	CS2_CLK => open,
	CT1 => open,
	CT1_CLK => open,
	TP => LAN1_TP
);

-- hardware test: read PHY_ID
SREG(8) <= LAN1_PHY_ID(7 downto 0);
-- fake input (to prevent optimization out). We need the pu/pd in .ucf
SREG(36)(6) <= LAN_CLK125;

--//-- IP STACK #1  -----------------------------------
-- 2 TCP connections
-- TCP Port 1028 reserved for monitoring & control
-- TCP Port 1024 for user application
-- 1 transmit UDP 
-- reclock with CLK_P for easier P&R
RECLOCK_IP2: process(CLK_P)
begin
	if rising_edge(CLK_P) then
		if(CONFIG_CHANGE_PULSE = '1') then
			IP2_ADDRv4(31 downto 0) <= CREG(41) & CREG(42) & CREG(43) & CREG(44);	-- local IP address
			LAN1_UDP_TX_DEST_IP_ADDR(31 downto 0) <= CREG(45) & CREG(46) & CREG(47) & CREG(48); 
			LAN1_UDP_TX_DEST_PORT_NO1 <= CREG(50) & CREG(49);
			SUBNET_MASK <= CREG(51) & CREG(52) & CREG(53) & CREG(54);
			GATEWAY_IP_ADDR <= CREG(55) & CREG(56) & CREG(57) & CREG(58);
			MULTICAST_IP_ADDR <= x"00000000";	-- unused here
		end if;
	end if;
end process;

IPSTACK_001: COM5402 
GENERIC MAP(
		NUDPTX => 1,
		NUDPRX => 0,
		NTCPSTREAMS => NTCPSTREAMS2,  
		CLK_FREQUENCY => CLK_FREQUENCY,	-- CLK_P 125 MHz, as time reference
		TX_IDLE_TIMEOUT => 50,	-- 50*4us = 200us 
		SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK_P,
	ASYNC_RESET => SYNC_RESET_CLK_P,
	SYNC_RESET => SYNC_RESET_CLK_P,
	MAC_ADDR => LAN1_MAC_ADDR,
	IPv4_ADDR => IP2_ADDRv4,
	IPv6_ADDR => x"00000000000000000000000000000000",
	SUBNET_MASK => SUBNET_MASK,
	MULTICAST_IP_ADDR => MULTICAST_IP_ADDR,
    GATEWAY_IP_ADDR => GATEWAY_IP_ADDR,
	CONNECTION_RESET => "00",
	-- MAC interface
	MAC_TX_DATA => LAN1_MAC_TX_DATA,
	MAC_TX_DATA_VALID => LAN1_MAC_TX_DATA_VALID,
	MAC_TX_EOF => LAN1_MAC_TX_EOF,
	MAC_TX_CTS => LAN1_MAC_TX_CTS,
	MAC_RX_DATA => LAN1_MAC_RX_DATA,
	MAC_RX_DATA_VALID => LAN1_MAC_RX_DATA_VALID,
	MAC_RX_SOF => LAN1_MAC_RX_SOF,
	MAC_RX_EOF => LAN1_MAC_RX_EOF,
	-- UDP rx
	UDP_RX_DATA => open,
	UDP_RX_DATA_VALID => open,
	UDP_RX_SOF => open,
	UDP_RX_EOF => open,
	UDP_RX_DEST_PORT_NO_IN => x"0000",
	CHECK_UDP_RX_DEST_PORT_NO => '0',
	UDP_RX_DEST_PORT_NO_OUT => open,
	-- UDP tx
	UDP_TX_DATA => LAN1_UDP_TX_DATA,
	UDP_TX_DATA_VALID => LAN1_UDP_TX_DATA_VALID,
	UDP_TX_SOF => LAN1_UDP_TX_SOF,
	UDP_TX_EOF => LAN1_UDP_TX_EOF,
	UDP_TX_CTS => LAN1_UDP_TX_CTS,
	UDP_TX_ACK => LAN1_UDP_TX_ACK,
	UDP_TX_NAK => LAN1_UDP_TX_NAK,
	UDP_TX_DEST_IP_ADDR => LAN1_UDP_TX_DEST_IP_ADDR,
	UDP_TX_DEST_PORT_NO => LAN1_UDP_TX_DEST_PORT_NO,
	UDP_TX_SOURCE_PORT_NO => x"0402",	-- 1026
	-- TCP rx streams
	TCP_RX_DATA => LAN1_TCP_RX_DATA,
	TCP_RX_DATA_VALID => LAN1_TCP_RX_DATA_VALID,
	TCP_RX_RTS => open,
	TCP_RX_CTS => LAN1_TCP_RX_CTS,	
	-- TCP tx streams
	TCP_TX_DATA => LAN1_TCP_TX_DATA,
	TCP_TX_DATA_VALID => LAN1_TCP_TX_DATA_VALID,
	TCP_TX_CTS => LAN1_TCP_TX_CTS,	
	-- Monitoring
--	CS1 => S1_1,
--	CS1_CLK => S1_1_CLK,
--	CS2 => S2_1,
--	CS2_CLK => S2_1_CLK,
	TP => IPSTACK2_TP	
);

-- one elastic buffer for each tcp rx stream
-- M&C, TCP port 1028 (port is defined within COM5402 component)
ELASTIC_BUFFER_NRAMB_002: ELASTIC_BUFFER_NRAMB 
generic map(
	NRAMB => 1,
	NBITS => 9,
	READ_AHEAD_1ADDRESS => '1'	-- no read latency, tricky timing ok because ARM is slower.
)
PORT MAP(
	CLK => CLK_P,
	SYNC_RESET => SYNC_RESET_CLK_P,
	DATA_IN => "0" & LAN1_TCP_RX_DATA(0),	-- 9 bit wide
	SAMPLE_CLK_IN => LAN1_TCP_RX_DATA_VALID(0),
	SAMPLE_CLK_IN_REQ => LAN1_TCP_RX_CTS(0),
	DATA_OUT => LAN1_RX_DATA1_X,	-- 9 bit wide
	SAMPLE_CLK_OUT => open,
	SAMPLE_CLK_OUT_E => open,
	SAMPLE_CLK_OUT_REQ => RX_LAN_SAMPLE_CLK_REQ,
	BUFFER_EMPTY => RX_LAN_BUFFER_EMPTY
);
RX_LAN <= LAN1_RX_DATA1_X(7 downto 0);

-- TCP port 1024
LAN1_TCP_RX_CTS(1) <= '1';

--//-- DDR3 SODIMM CONTROLLER  -----------------------------------------------
DDR3_CONTROLLER_001: if (DDR3_ENABLED = '1') generate

	-- test sequencer
	DDR3_WR_ADDR_PLUS8 <= DDR3_WR_ADDR + 8;	-- because burst length BL=8
	DDR3_RD_ADDR_PLUS8 <= DDR3_RD_ADDR + 8;
	DDR3_STARTADDR <= CREG(3) & CREG(2) & CREG(1) & CREG(0); -- inclusive 
	DDR3_CEILINGADDR <= CREG(7) & CREG(6) & CREG(5) & CREG(4); -- exclusive
	DDR3_TEST_STATE_GEN_001: process(CLK_P)
	begin
		if rising_edge(CLK_P) then
			if(SYNC_RESET_CLK_P = '1') then
				DDR3_TEST_STATE <= 0;
			elsif(DDR3_MEMORY_RDY_OUT = '1') and (CONFIG_CHANGE_PULSE = '1') and (CREG(10)(2 downto 0) = "010") then
				-- immediate stop any ongoing write transaction (from any state)
				DDR3_TEST_STATE <= 5;
				DDR3_DATA1_IN_SETADDR <= '1';
				DDR3_DATA1_IN_MODE <= "11";
			elsif(DDR3_TEST_STATE = 5) then
				-- end of terminate transaction
				DDR3_TEST_STATE <= 0;
				DDR3_DATA1_IN_SETADDR <= '0';

			elsif(DDR3_MEMORY_RDY_OUT = '1') and (CONFIG_CHANGE_PULSE = '1') and (CREG(10)(2 downto 0) = "100") then
				-- immediate stop any current ongoing read transaction (from any state)
				DDR3_TEST_STATE <= 6;
				DDR3_DATA1_OUT_SETADDR <= '1';
				DDR3_DATA1_OUT_MODE <= "11";
			elsif(DDR3_TEST_STATE = 6) then
				-- end of terminate transaction
				DDR3_TEST_STATE <= 0;
				DDR3_DATA1_OUT_SETADDR <= '0';


			elsif(DDR3_TEST_STATE = 0) and (DDR3_MEMORY_RDY_OUT = '1') and (CONFIG_CHANGE_PULSE = '1') and (CREG(10)(2 downto 0) = "001") then
--			elsif(DDR3_TEST_STATE = 0) and (DDR3_MEMORY_RDY_OUT = '1') then
				-- send write command
				DDR3_TEST_STATE <= 1;
				DDR3_DATA1_IN_SETADDR <= '1';
				DDR3_DATA1_IN_STARTADDR <= DDR3_STARTADDR;	-- inclusive 
				DDR3_DATA1_IN_CEILINGADDR <= DDR3_CEILINGADDR;	-- exclusive
				DDR3_DATA1_IN(15 downto 0) <= (others => '1');
				DDR3_DATA1_IN(15+64 downto 64) <= (others => '1');
				DDR3_DATA1_IN(15+2*64 downto 2*64) <= (others => '1');
				DDR3_DATA1_IN(15+3*64 downto 3*64) <= (others => '1');
				DDR3_DATA1_IN(15+4*64 downto 4*64) <= (others => '1');
				DDR3_DATA1_IN(15+5*64 downto 5*64) <= (others => '1');
				DDR3_DATA1_IN(15+6*64 downto 6*64) <= (others => '1');
				DDR3_DATA1_IN(15+7*64 downto 7*64) <= (others => '1');
				DDR3_DATA1_IN_MODE <= "10";
			elsif(DDR3_TEST_STATE = 1) then
				DDR3_DATA1_IN_SETADDR <= '0';
				DDR3_TEST_STATE <= 2;
				DDR3_WR_ADDR <= unsigned(DDR3_DATA1_IN_STARTADDR) - 1;	-- count number of input words. must be consistent with start/ceiling
			elsif(DDR3_TEST_STATE = 2) then
				if(DDR3_WR_ADDR_PLUS8 >= unsigned(DDR3_DATA1_IN_CEILINGADDR)) then
					DDR3_TEST_STATE <= 0;
					DDR3_DATA1_IN_VALID <= '0';
				elsif(DDR3_DATA1_IN_CTS = '1') then
					DDR3_WR_ADDR <= DDR3_WR_ADDR_PLUS8;
					DDR3_DATA1_IN(15+0*64 downto 0*64) <= std_logic_vector(unsigned(DDR3_DATA1_IN(15+0*64 downto 0*64)) + 1);
					DDR3_DATA1_IN(15+1*64 downto 1*64) <= std_logic_vector(unsigned(DDR3_DATA1_IN(15+1*64 downto 1*64)) - 1);
					DDR3_DATA1_IN(15+2*64 downto 2*64) <= std_logic_vector(unsigned(DDR3_DATA1_IN(15+2*64 downto 2*64)) + 2);
					DDR3_DATA1_IN(15+3*64 downto 3*64) <= std_logic_vector(unsigned(DDR3_DATA1_IN(15+3*64 downto 3*64)) - 2);
					DDR3_DATA1_IN(15+4*64 downto 4*64) <= std_logic_vector(unsigned(DDR3_DATA1_IN(15+4*64 downto 4*64)) + 3);
					DDR3_DATA1_IN(15+5*64 downto 5*64) <= std_logic_vector(unsigned(DDR3_DATA1_IN(15+5*64 downto 5*64)) - 3);
					DDR3_DATA1_IN(15+6*64 downto 6*64) <= std_logic_vector(unsigned(DDR3_DATA1_IN(15+6*64 downto 6*64)) + 5);
					DDR3_DATA1_IN(15+7*64 downto 7*64) <= std_logic_vector(unsigned(DDR3_DATA1_IN(15+7*64 downto 7*64)) - 5);
					DDR3_DATA1_IN_VALID <= '1';
				else
					DDR3_DATA1_IN_VALID <= '0';
				end if;

				
				
--			elsif(DDR3_TEST_STATE = 3) and (DDR3_WRITE_COMMAND_COMPLETE = '1')  then
-- doubt about DDR3_WRITE_COMMAND_COMPLETE
			elsif(DDR3_TEST_STATE = 0) and (CONFIG_CHANGE_PULSE = '1') and (CREG(10)(2 downto 0) = "011") then
				-- send read command
				DDR3_TEST_STATE <= 4;
				DDR3_DATA1_OUT_SETADDR <= '1';
				DDR3_DATA1_OUT_STARTADDR <= DDR3_STARTADDR;	-- inclusive 
				DDR3_DATA1_OUT_CEILINGADDR <= DDR3_CEILINGADDR;	-- exclusive
				DDR3_DATA1_OUT_MODE <= "10";
				DDR3_RD_ADDR <= unsigned(DDR3_STARTADDR);	-- inclusive 
			elsif(DDR3_TEST_STATE = 4) then
				DDR3_DATA1_OUT_SETADDR <= '0';
				if(DDR3_RD_ADDR_PLUS8 >= unsigned(DDR3_DATA1_OUT_CEILINGADDR)) then
					DDR3_TEST_STATE <= 0;
				elsif(DDR3_DATA1_OUT_VALID = '1') then
					DDR3_RD_ADDR <= DDR3_RD_ADDR_PLUS8;
				end if;

			end if;
		end if;
	end process;
	
	SREG(10) <= std_logic_vector(DDR3_RD_ADDR(31 downto 24));
	SREG(11) <= std_logic_vector(DDR3_RD_ADDR(23 downto 16));
	SREG(12) <= std_logic_vector(DDR3_RD_ADDR(15 downto 8));
	SREG(13) <= std_logic_vector(DDR3_RD_ADDR(7 downto 0));
	SREG(14) <= DDR3_DATA1_OUT_ADDR(31 downto 24);
	SREG(15) <= DDR3_DATA1_OUT_ADDR(23 downto 16);
	SREG(16) <= DDR3_DATA1_OUT_ADDR(15 downto 8);
	SREG(17) <= DDR3_DATA1_OUT_ADDR(7 downto 0);
	SREG(18) <= DDR3_DATA1_OUT_CEILINGADDR(31 downto 24);
	SREG(19) <= DDR3_DATA1_OUT_CEILINGADDR(23 downto 16);
	SREG(20) <= DDR3_DATA1_OUT_CEILINGADDR(15 downto 8);
	SREG(21) <= DDR3_DATA1_OUT_CEILINGADDR(7 downto 0);
	SREG(22) <= std_logic_vector(to_unsigned(DDR3_TEST_STATE,8));
--	-- capture the first read word and copy to status registers
--	CAPTURE_001: process(CLK_P)
--	begin
--		if rising_edge(CLK_P) then
--			if(DDR3_TEST_STATE = 0) and (CONFIG_CHANGE_PULSE = '1') and (CREG(10)(2 downto 0) = "011") then
--				-- arm first read word flag
--				FIRST_READ_WORD_FLAG <= '1';
--			elsif(FIRST_READ_WORD_FLAG = '1') and (DDR3_DATA1_OUT_VALID = '1') then
--				FIRST_READ_WORD_FLAG <= '0';
--				for I in 0 to 7 loop
--					SREG(10 + I) <= DDR3_DATA1_OUT(((8*(I+1)) - 1) downto 8*I);
--				end loop;
--			end if;
--		end if;
--	end process;
--				

	
DDR3_DATA1_OUT_CTS <= '1';

	DDR3_WRAPPER_001: DDR3_WRAPPER 
	GENERIC MAP(
		DDR3_NRANKS => DDR3_NRANKS,
		DDR3_NADDRBITS => DDR3_NADDRBITS,
		APP_NADDRBITS => APP_NADDRBITS,
		SIMULATION => SIMULATION
	 ) 
	PORT MAP(
		CLK => CLK_P,
		SYNC_RESET => SYNC_RESET_CLK_P,
		CLKREF_IN => CLKREF25Cg,
		DATA1_IN => DDR3_DATA1_IN,
		DATA1_IN_VALID => DDR3_DATA1_IN_VALID,
		DATA1_IN_CTS => DDR3_DATA1_IN_CTS,
		DATA1_IN_SETADDR => DDR3_DATA1_IN_SETADDR,
		DATA1_IN_STARTADDR => DDR3_DATA1_IN_STARTADDR,
		DATA1_IN_CEILINGADDR => DDR3_DATA1_IN_CEILINGADDR,
		DATA1_IN_MODE => DDR3_DATA1_IN_MODE,
		WRITE_COMMAND_COMPLETE => DDR3_WRITE_COMMAND_COMPLETE,
		DATA1_OUT => DDR3_DATA1_OUT,
		DATA1_OUT_VALID => DDR3_DATA1_OUT_VALID,
		DATA1_OUT_CTS => DDR3_DATA1_OUT_CTS,
		DATA1_OUT_EMPTY => DDR3_DATA1_OUT_EMPTY,
		DATA1_OUT_SETADDR => DDR3_DATA1_OUT_SETADDR,
		DATA1_OUT_STARTADDR => DDR3_DATA1_OUT_STARTADDR,
		DATA1_OUT_CEILINGADDR => DDR3_DATA1_OUT_CEILINGADDR,
		DATA1_OUT_MODE => DDR3_DATA1_OUT_MODE,
		ddr3_dq => ddr3_dq,
		ddr3_dqs_p => ddr3_dqs_p,
		ddr3_dqs_n => ddr3_dqs_n,
		ddr3_addr => ddr3_addr,
		ddr3_ba => ddr3_ba,
		ddr3_ras_n => ddr3_ras_n,
		ddr3_cas_n => ddr3_cas_n,
		ddr3_we_n => ddr3_we_n,
		ddr3_reset_n => ddr3_reset_n,
		ddr3_ck_p => ddr3_ck_p,
		ddr3_ck_n => ddr3_ck_n,
		ddr3_cke => ddr3_cke,
		ddr3_cs_n => ddr3_cs_n,
		ddr3_dm => ddr3_dm,
		ddr3_odt => ddr3_odt,
		PLL_LOCKED_OUT => DDR3_PLL_LOCKED_OUT,
		MEMORY_RDY_OUT => DDR3_MEMORY_RDY_OUT,
		DATA1_IN_ADDR => DDR3_DATA1_IN_ADDR,	-- may not be timely (waiting for idle to cross clock domains)
		DATA1_OUT_ADDR => DDR3_DATA1_OUT_ADDR,
		TP => DDR3_TP
	);
end generate;

--// COM-30xx RF RECEIVER  -----------------------------------------------
-- optional RF receiver connected through the right (J8) connector
-- comment out if not applicable
-- Mutually exclusive with COM2802_ENABLED below
OPTIONAL_COM30XX_J8: if(COM30XX_J8_ENABLED = '1') generate
	-- generate a 99 MHz ADC sampling clock for the RF receiver
  mmcm_adv_inst : MMCME2_ADV
  generic map
   (BANDWIDTH            => "OPTIMIZED",
    CLKOUT4_CASCADE      => FALSE,
    COMPENSATION         => "ZHOLD",
    STARTUP_WAIT         => FALSE,
    DIVCLK_DIVIDE        => 1,
    CLKFBOUT_MULT_F      => 62.000,	
    CLKFBOUT_PHASE       => 0.000,
    CLKFBOUT_USE_FINE_PS => FALSE,
    CLKOUT0_DIVIDE_F     => 6.250,
    CLKOUT0_PHASE        => 0.000,
    CLKOUT0_DUTY_CYCLE   => 0.500, -- other duty cycle not supported because DIVIDE_F is a float
    CLKOUT0_USE_FINE_PS  => FALSE,
    CLKIN1_PERIOD        => 100.000,
    REF_JITTER1          => 0.001)
  port map
    -- Output clocks
   (CLKFBOUT            => clkfbout,
    CLKFBOUTB           => open,
    CLKOUT0             => CLK99,
    CLKOUT0B            => open,
    CLKOUT1             => open,
    CLKOUT1B            => open,
    CLKOUT2             => open,
    CLKOUT2B            => open,
    CLKOUT3             => open,
    CLKOUT3B            => open,
    CLKOUT4             => open,
    CLKOUT5             => open,
    CLKOUT6             => open,
    -- Input clock control
    CLKFBIN             => clkfbout,
    CLKIN1              => CLK10g,
    CLKIN2              => '0',
    -- Tied to always select the primary input clock
    CLKINSEL            => '1',
    -- Ports for dynamic reconfiguration
    DADDR               => (others => '0'),
    DCLK                => '0',
    DEN                 => '0',
    DI                  => (others => '0'),
    DO                  => open,
    DRDY                => open,
    DWE                 => '0',
    -- Ports for dynamic phase shift
    PSCLK               => '0',
    PSEN                => '0',
    PSINCDEC            => '0',
    PSDONE              => open,
    -- Other control and status signals
    LOCKED              => open,
    CLKINSTOPPED        => open,
    CLKFBSTOPPED        => open,
    PWRDWN              => '0',
    RST                 => '0');


	TP1 : ODDR
	generic map(
		DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 
		INIT => '0',   -- Initial value for Q port ('1' or '0')
		SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
	port map (
		Q => RIGHT_CONNECTOR_A(14),   -- 1-bit DDR output
		C => CLK99,    -- 1-bit clock input
		CE => '1',  -- 1-bit clock enable input
		D1 => '1',  -- 1-bit data input (positive edge)
		D2 => '0',  -- 1-bit data input (negative edge)
		R => '0',    -- 1-bit reset input
		S => '0'     -- 1-bit set input
	);


end generate;

--// COM-2802 QUAD DDS DRIVER  -----------------------------------------------
-- optional quad DDS synthesizers through the right (J8) connector
-- comment out if not applicable
-- Mutually exclusive with COM30XX_J8_ENABLED below
OPTIONAL_COM2802: if(COM2802_ENABLED = '1') generate

IBUF_001A: BUFG port map(I => RIGHT_CONNECTOR_A(1), O => DDSA_CLK_IN);  
IBUF_001B: BUFG port map(I => RIGHT_CONNECTOR_A(19), O => DDSB_CLK_IN);  
IBUF_001C: BUFG port map(I => RIGHT_CONNECTOR_B1(1), O => DDSC_CLK_IN);  
IBUF_001D: BUFG port map(I => RIGHT_CONNECTOR_B3(21), O => DDSD_CLK_IN);  
-- depending on the clock frequency ADJUST DELAY HERE

    -- test test test
    -- generate test ramps
    TEST_RAMP_001: process(CLK_P)
    begin
        if rising_edge(CLK_P) then
            TR1 <= TR1 + 1;
            TR2 <= TR2 -1;
        end if;
    end process;

	COM2802A_OUTPUT_001: MUXED_OUTPUT_2DDS port map(
		CLK => CLK_P,
		SYNC_RESET => SYNC_RESET_CLK_P,
		DATA_I_IN => std_logic_vector(TR1),
		DATA_Q_IN => std_logic_vector(TR2),
		TX_ENABLE_IN => '1',
		DDS_CLK_IN => DDSA_CLK_IN,	-- input clock from COM-2802 (2x sampling rate)
		DATA_OUT => COM2802A_DOUT,	-- 16-bit output, unsigned (offset binary)
		TX_ENABLE_OUT => COM2802A_TX_ENABLE_OUT
		);

	COM2802B_OUTPUT_001: MUXED_OUTPUT_2DDS port map(
		CLK => CLK_P,
		SYNC_RESET => SYNC_RESET_CLK_P,
		DATA_I_IN => std_logic_vector(TR1),
		DATA_Q_IN => std_logic_vector(TR2),
		TX_ENABLE_IN => '1',
		DDS_CLK_IN => DDSB_CLK_IN,	-- input clock from COM-2802 (2x sampling rate)
		DATA_OUT => COM2802B_DOUT,	-- 16-bit output, unsigned (offset binary)
		TX_ENABLE_OUT => COM2802B_TX_ENABLE_OUT
		);

	COM2802C_OUTPUT_001: MUXED_OUTPUT_2DDS port map(
		CLK => CLK_P,
		SYNC_RESET => SYNC_RESET_CLK_P,
		DATA_I_IN => std_logic_vector(TR1),
		DATA_Q_IN => std_logic_vector(TR2),
		TX_ENABLE_IN => '1',
		DDS_CLK_IN => DDSC_CLK_IN,	-- input clock from COM-2802 (2x sampling rate)
		DATA_OUT => COM2802C_DOUT,	-- 16-bit output, unsigned (offset binary)
		TX_ENABLE_OUT => COM2802C_TX_ENABLE_OUT
		);

	COM2802D_OUTPUT_001: MUXED_OUTPUT_2DDS port map(
		CLK => CLK_P,
		SYNC_RESET => SYNC_RESET_CLK_P,
		DATA_I_IN => std_logic_vector(TR1),
		DATA_Q_IN => std_logic_vector(TR2),
		TX_ENABLE_IN => '1',
		DDS_CLK_IN => DDSD_CLK_IN,	-- input clock from COM-2802 (2x sampling rate)
		DATA_OUT => COM2802D_DOUT,	-- 16-bit output, unsigned (offset binary)
		TX_ENABLE_OUT => COM2802D_TX_ENABLE_OUT
		);
		
	RIGHT_CONNECTOR_A(2) <= COM2802A_TX_ENABLE_OUT;
	RIGHT_CONNECTOR_A(3) <= COM2802A_DOUT(15);	
	RIGHT_CONNECTOR_A(4) <= COM2802A_DOUT(14);	
	RIGHT_CONNECTOR_A(5) <= COM2802A_DOUT(13);	
	RIGHT_CONNECTOR_A(6) <= COM2802A_DOUT(12);	
	RIGHT_CONNECTOR_A(7) <= COM2802A_DOUT(11);	
	RIGHT_CONNECTOR_A(8) <= COM2802A_DOUT(10);	
	RIGHT_CONNECTOR_A(9) <= COM2802A_DOUT(9);	
	RIGHT_CONNECTOR_A(10) <= COM2802A_DOUT(8);	
	RIGHT_CONNECTOR_A(11) <= COM2802A_DOUT(7);	
	RIGHT_CONNECTOR_A(12) <= COM2802A_DOUT(6);	
	RIGHT_CONNECTOR_A(13) <= COM2802A_DOUT(5);	
	RIGHT_CONNECTOR_A(14) <= COM2802A_DOUT(4);	
	RIGHT_CONNECTOR_A(15) <= COM2802A_DOUT(3);	
	RIGHT_CONNECTOR_A(16) <= COM2802A_DOUT(2);	
	RIGHT_CONNECTOR_A(17) <= COM2802A_DOUT(1);	
	RIGHT_CONNECTOR_A(18) <= COM2802A_DOUT(0);	
	
	RIGHT_CONNECTOR_A(20) <= COM2802B_TX_ENABLE_OUT;
    RIGHT_CONNECTOR_A(21) <= COM2802B_DOUT(15);    
    RIGHT_CONNECTOR_A(22) <= COM2802B_DOUT(14);    
    RIGHT_CONNECTOR_A(23) <= COM2802B_DOUT(13);    
    RIGHT_CONNECTOR_A(24) <= COM2802B_DOUT(12);    
    RIGHT_CONNECTOR_A(25) <= COM2802B_DOUT(11);    
    RIGHT_CONNECTOR_A(26) <= COM2802B_DOUT(10);    
    RIGHT_CONNECTOR_A(27) <= COM2802B_DOUT(9);    
    RIGHT_CONNECTOR_A(28) <= COM2802B_DOUT(8);    
    RIGHT_CONNECTOR_A(29) <= COM2802B_DOUT(7);    
    RIGHT_CONNECTOR_A(30) <= COM2802B_DOUT(6);    
    RIGHT_CONNECTOR_A(31) <= COM2802B_DOUT(5);    
    RIGHT_CONNECTOR_A(32) <= COM2802B_DOUT(4);    
    RIGHT_CONNECTOR_A(33) <= COM2802B_DOUT(3);    
    RIGHT_CONNECTOR_A(34) <= COM2802B_DOUT(2);    
    RIGHT_CONNECTOR_A(35) <= COM2802B_DOUT(1);    
    RIGHT_CONNECTOR_A(36) <= COM2802B_DOUT(0);    

	RIGHT_CONNECTOR_B1(2) <= COM2802C_TX_ENABLE_OUT;
	RIGHT_CONNECTOR_B1(3) <= COM2802C_DOUT(15);	
	RIGHT_CONNECTOR_B1(4) <= COM2802C_DOUT(14);	
	RIGHT_CONNECTOR_B2(6) <= COM2802C_DOUT(13);	
	RIGHT_CONNECTOR_B2(7) <= COM2802C_DOUT(12);	
	RIGHT_CONNECTOR_B2(8) <= COM2802C_DOUT(11);	
	RIGHT_CONNECTOR_B2(9) <= COM2802C_DOUT(10);	
	RIGHT_CONNECTOR_B2(10) <= COM2802C_DOUT(9);	
	RIGHT_CONNECTOR_B2(11) <= COM2802C_DOUT(8);	
	RIGHT_CONNECTOR_B2(12) <= COM2802C_DOUT(7);	
	RIGHT_CONNECTOR_B2(13) <= COM2802C_DOUT(6);	
	RIGHT_CONNECTOR_B2(14) <= COM2802C_DOUT(5);	
	RIGHT_CONNECTOR_B2(15) <= COM2802C_DOUT(4);	
	RIGHT_CONNECTOR_B2(16) <= COM2802C_DOUT(3);	
	RIGHT_CONNECTOR_B2(17) <= COM2802C_DOUT(2);	
	RIGHT_CONNECTOR_B2(18) <= COM2802C_DOUT(1);	
	RIGHT_CONNECTOR_B2(19) <= COM2802C_DOUT(0);	

	RIGHT_CONNECTOR_B3(22) <= COM2802D_TX_ENABLE_OUT;
	RIGHT_CONNECTOR_B3(23) <= COM2802D_DOUT(15);	
	RIGHT_CONNECTOR_B3(24) <= COM2802D_DOUT(14);	
	RIGHT_CONNECTOR_B3(25) <= COM2802D_DOUT(13);	
	RIGHT_CONNECTOR_B3(26) <= COM2802D_DOUT(12);	
	RIGHT_CONNECTOR_B3(27) <= COM2802D_DOUT(11);	
	RIGHT_CONNECTOR_B3(28) <= COM2802D_DOUT(10);	
	RIGHT_CONNECTOR_B3(29) <= COM2802D_DOUT(9);	
	RIGHT_CONNECTOR_B3(30) <= COM2802D_DOUT(8);	
	RIGHT_CONNECTOR_B4(32) <= COM2802D_DOUT(7);	
	RIGHT_CONNECTOR_B4(33) <= COM2802D_DOUT(6);	
	RIGHT_CONNECTOR_B4(34) <= COM2802D_DOUT(5);	
	RIGHT_CONNECTOR_B4(35) <= COM2802D_DOUT(4);	
	RIGHT_CONNECTOR_B4(36) <= COM2802D_DOUT(3);	
	RIGHT_CONNECTOR_B4(37) <= COM2802D_DOUT(2);	
	RIGHT_CONNECTOR_B4(38) <= COM2802D_DOUT(1);	
	RIGHT_CONNECTOR_B4(39) <= COM2802D_DOUT(0);	
	
end generate;





--// TEST POINTS  -----------------------------------------------
-- Warning: test points can make timing much worse!
--	TP_GEN_001: process(CLK_P)
--	begin
--		 if rising_edge(CLK_P) then
--			RIGHT_CONNECTOR_A(1) <= '0';	
--			RIGHT_CONNECTOR_A(2) <= '0';	
--		 end if;
--	end process;

--LEFT_CONNECTOR_A(20 downto 2) <= DDR3_TP(20 downto 2);
--	
--TP1 : ODDR
--generic map(
--	DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 
--	INIT => '0',   -- Initial value for Q port ('1' or '0')
--	SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
--port map (
--	Q => LEFT_CONNECTOR_A(1),   -- 1-bit DDR output
--	C => DDR3_TP(1),    -- 1-bit clock input
--	CE => '1',  -- 1-bit clock enable input
--	D1 => '1',  -- 1-bit data input (positive edge)
--	D2 => '0',  -- 1-bit data input (negative edge)
--	R => '0',    -- 1-bit reset input
--	S => '0'     -- 1-bit set input
--);

--LEFT_CONNECTOR_A(1) <= CLKGEN7C_INPUT_CLK_STOPPED;
--LEFT_CONNECTOR_A(2) <= CLKGEN7C_LOCKED;
--LEFT_CONNECTOR_A(3) <= CLKGEN7D_INPUT_CLK_STOPPED;
--LEFT_CONNECTOR_A(4) <= CLKGEN7D_LOCKED;
--LEFT_CONNECTOR_A(5) <= DDR3_PLL_LOCKED_OUT;
--TP1 : ODDR
--generic map(
--	DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 
--	INIT => '0',   -- Initial value for Q port ('1' or '0')
--	SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
--port map (
--	Q => LEFT_CONNECTOR_A(6),   -- 1-bit DDR output
--	C => CLKREF25Cg,    -- 1-bit clock input
--	CE => '1',  -- 1-bit clock enable input
--	D1 => '1',  -- 1-bit data input (positive edge)
--	D2 => '0',  -- 1-bit data input (negative edge)
--	R => '0',    -- 1-bit reset input
--	S => '0'     -- 1-bit set input
--);
--LEFT_CONNECTOR_A(15 downto 1) <= DDR3_TP(15 downto 1); -- check phase noise with a spectrum analyzer
--LEFT_CONNECTOR_A(16) <= CONFIG_CHANGE_PULSE;
--LEFT_CONNECTOR_A(17) <= DDR3_DATA1_IN_SETADDR;
--LEFT_CONNECTOR_A(18) <= '1' when (DDR3_TEST_STATE = 0) else '0';
--LEFT_CONNECTOR_A(19) <= '1' when (DDR3_TEST_STATE = 2) else '0';
--LEFT_CONNECTOR_A(20) <= '1' when (DDR3_TEST_STATE = 4) else '0';
--LEFT_CONNECTOR_A(21) <= '1' when (DDR3_TEST_STATE = 5) else '0';
--LEFT_CONNECTOR_A(22) <= '1' when (DDR3_TEST_STATE = 6) else '0';

LEFT_CONNECTOR_A(10 downto 1) <= COMSCOPE2_TP;
LEFT_CONNECTOR_A(11) <= PLL25_LOCKED;
TP1 : ODDR
generic map(
	DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 
	INIT => '0',   -- Initial value for Q port ('1' or '0')
	SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
	Q => LEFT_CONNECTOR_A(12),   -- 1-bit DDR output
	C => CLKREF25Cg,    -- 1-bit clock input
	CE => '1',  -- 1-bit clock enable input
	D1 => '1',  -- 1-bit data input (positive edge)
	D2 => '0',  -- 1-bit data input (negative edge)
	R => '0',    -- 1-bit reset input
	S => '0'     -- 1-bit set input
);



--LEFT_CONNECTOR_A(1) <= CONFIG_CHANGE_PULSE;
--LEFT_CONNECTOR_A(2) <= DDR3_DATA1_IN_SETADDR;
--LEFT_CONNECTOR_A(3) <= DDR3_WRITE_COMMAND_COMPLETE;
--LEFT_CONNECTOR_A(4) <= DDR3_DATA1_IN_CTS;
--LEFT_CONNECTOR_A(5) <= DDR3_DATA1_IN_VALID;
--LEFT_CONNECTOR_A(6) <= '1' when (DDR3_TEST_STATE = 0) else '0';
--LEFT_CONNECTOR_A(7) <= '1' when (DDR3_TEST_STATE = 2) else '0';
--LEFT_CONNECTOR_A(8) <= '1' when (DDR3_TEST_STATE = 4) else '0';
--LEFT_CONNECTOR_A(9) <= '1' when (DDR3_TEST_STATE = 5) else '0';
--LEFT_CONNECTOR_A(10) <= '1' when (DDR3_TEST_STATE = 6) else '0';
--LEFT_CONNECTOR_A(11) <= DDR3_DATA1_OUT_SETADDR;
--LEFT_CONNECTOR_A(12) <= DDR3_DATA1_OUT_VALID;
--LEFT_CONNECTOR_A(13) <= DDR3_TP(13);	-- event3 writing
--LEFT_CONNECTOR_A(14) <= DDR3_TP(14);	-- event4 input elastic buffer empty. end of write?
--LEFT_CONNECTOR_A(15) <= DDR3_TP(15);	-- event5 write accepted
--LEFT_CONNECTOR_A(16) <= DDR3_TP(17);	-- event7
--LEFT_CONNECTOR_A(17) <= DDR3_TP(18);	-- event8
--LEFT_CONNECTOR_A(18) <= DDR3_TP(19);	-- event9 end of read
--LEFT_CONNECTOR_A(19) <= DDR3_TP(6);	-- app_rdy
--LEFT_CONNECTOR_A(20) <= DDR3_TP(8);	-- app_rd_data_valid
	
	
	
--// COMSCOPE2 -----------------------------------------------------
	-- Define Comscope traces here 
	-- Trace 1, connect as needed
	
	S1_1 <= DDR3_DATA1_OUT(0*64+7 downto 0*64);		
	S1_1_CLK <= DDR3_DATA1_OUT_VALID;
	S1_2 <= DDR3_DATA1_OUT(1*64+7 downto 1*64);		
	S1_2_CLK <= DDR3_DATA1_OUT_VALID;
	S1_3 <= DDR3_DATA1_OUT(2*64+7 downto 2*64);		
	S1_3_CLK <= DDR3_DATA1_OUT_VALID;
	S1_4 <= DDR3_DATA1_OUT(3*64+7 downto 3*64);		
	S1_4_CLK <= DDR3_DATA1_OUT_VALID;
	--S1_2, S1_3, S1_4, etc 	

	-- Trace 2
	S2_1 <= DDR3_DATA1_OUT(4*64+7 downto 4*64);		
	S2_1_CLK <= DDR3_DATA1_OUT_VALID;
	S2_2 <= DDR3_DATA1_OUT(5*64+7 downto 5*64);		
	S2_2_CLK <= DDR3_DATA1_OUT_VALID;
	S2_3 <= DDR3_DATA1_OUT(6*64+7 downto 6*64);		
	S2_3_CLK <= DDR3_DATA1_OUT_VALID;
	S2_4 <= DDR3_DATA1_OUT(7*64+7 downto 7*64);		
	S2_4_CLK <= DDR3_DATA1_OUT_VALID;
	--S2_2, S2_3, S2_4, etc

	COMSCOPE2_001: COMSCOPE2 
	generic map(
		TRACE1_ENABLED => '1',    -- enable as many simultaneous traces as needed
		TRACE2_ENABLED => '1',
		TRACE3_ENABLED => '0',
		TRACE4_ENABLED => '0',
		DATA_WIDTH1A => 8,
		ADDR_WIDTH1A => 9,
		ADDR_WIDTH1B => 9,
		DATA_WIDTH2A => 8,
		ADDR_WIDTH2A => 9,
		ADDR_WIDTH2B => 9,
		DATA_WIDTH3A => 8,
		ADDR_WIDTH3A => 9,
		ADDR_WIDTH3B => 9,
		DATA_WIDTH4A => 8,
		ADDR_WIDTH4A => 9,
		ADDR_WIDTH4B => 9
	)
	PORT MAP(
		CLK => CLK_P,
		SYNC_RESET => SYNC_RESET_CLK_P,
		REG238 => REG238,
		REG239 => x"00", --REG239,  acquire mode: sample
		REG240 => REG240,
		REG241 => REG241,
		REG242 => REG242,
		REG243 => REG243,
		REG244 => REG244,
		REG245 => REG245,
		REG246 => REG246,
		REG247 => REG247,
		REG248 => REG248,
		REG249 => REG249,
		S1_1 => S1_1,
		S1_1_VALID => S1_1_CLK,
		S1_2 => S1_2,
		S1_2_VALID => S1_2_CLK,
		S1_3 => S1_3,
		S1_3_VALID => S1_3_CLK,
		S1_4 => S1_4,
		S1_4_VALID => S1_4_CLK,
		S2_1 => S2_1,
		S2_1_VALID => S2_1_CLK,
		S2_2 => S2_2,
		S2_2_VALID => S2_2_CLK,
		S2_3 => S2_3,
		S2_3_VALID => S2_3_CLK,
		S2_4 => S2_4,
		S2_4_VALID => S2_4_CLK,
		S3_1 => (others => '0'),
		S3_1_VALID => '0',
		S3_2 => (others => '0'),
		S3_2_VALID => '0',
		S3_3 => (others => '0'),
		S3_3_VALID => '0',
		S3_4 => (others => '0'),
		S3_4_VALID => '0',
		S4_1 => (others => '0'),
		S4_1_VALID => '0',
		S4_2 => (others => '0'),
		S4_2_VALID => '0',
		S4_3 => (others => '0'),
		S4_3_VALID => '0',
		S4_4 => (others => '0'),
		S4_4_VALID => '0',
		T16b_1 => (others => '0'),
		T16b_1_VALID => '0',
		T16b_2 => (others => '0'),
		T16b_2_VALID => '0',
		T16b_3 => (others => '0'),
		T16b_3_VALID => '0',
		T16b_4 => (others => '0'),
		T16b_4_VALID => '0',
		SREG250 => REG250,
		SREG251 => REG251,
		TRIGGER_REARM_TOGGLE => TRIGGER_REARM_TOGGLE,
		FORCE_TRIGGER_TOGGLE => FORCE_TRIGGER_TOGGLE,
		SREG250_READ_TOGGLE => SREG250_READ_TOGGLE,
		START_CAPTURE_TOGGLE => START_CAPTURE_TOGGLE,
		TP => COMSCOPE2_TP
	);
	
	
--// COMSCOPE -----------------------------------------------------
--COMSCOPE_GEN: if (SIMULATION = '0') generate
--	--  Comment in/out as needed. unused during simulation
--	-- 
--
--	-- Trace 3  TODO
--
--	-- Trigger (1-bit format)
--    T1 <= '0';
--    T1_CLK <= '0';
--    
--	S1_1B_CLK <= S1_1_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
--	S1_2B_CLK <= S1_2_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
--	S1_3B_CLK <= S1_3_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
--	S1_4B_CLK <= S1_4_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
--
--	S2_1B_CLK <= S2_1_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
--	S2_2B_CLK <= S2_2_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
--	S2_3B_CLK <= S2_3_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
--	S2_4B_CLK <= S2_4_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
--
--	S3_1B_CLK <= S3_1_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
--	S3_2B_CLK <= S3_2_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
--	S3_3B_CLK <= S3_3_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
--	S3_4B_CLK <= S3_4_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
--
--	S4_1B_CLK <= S4_1_CLK or REG246(7);	-- Nominal sampling clock or real-time processing clock
--	S4_2B_CLK <= S4_2_CLK or REG246(7);	-- Nominal sampling clock or real-time processing clock
--	S4_3B_CLK <= S4_3_CLK or REG246(7);	-- Nominal sampling clock or real-time processing clock
--	S4_4B_CLK <= S4_4_CLK or REG246(7);	-- Nominal sampling clock or real-time processing clock
--
--	COMSCOPE_001: COMSCOPE 
--	generic map(
--		TRACE1_ENABLED => '1',    -- enable as many simultaneous traces as needed
--		TRACE2_ENABLED => '1',
--		TRACE3_ENABLED => '0',
--		TRACE4_ENABLED => '0'
--	)
--	port map(
--		CLK => CLK_P,
--		SYNC_RESET => SYNC_RESET_CLK_P,
--		SIGNED_REPRESENTATION_U_SIGNED_N => REG248(6),	-- trigger format signed(1) or unsigned(0)
--		REG237 => REG237,
--		REG238 => REG238,
--		REG239 => REG239,
--		REG240 => REG240,
--		REG241 => REG241,
--		REG242 => REG242,
--		REG243 => REG243,
--		REG244 => REG244,
--		REG245 => REG245,
--		REG246 => REG246,
--		REG247 => REG247,
--		REG248 => REG248,
--		REG249 => REG249,
--		SIGNAL_1_BIT_1_1 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_1_1 => '0',
--		SIGNAL_1_BIT_1_2 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_1_2 => '0',
--		SIGNAL_1_BIT_1_3 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_1_3 => '0',
--		SIGNAL_1_BIT_1_4 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_1_4 => '0',
--	--	SIGNAL_2_BIT_1_1 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_1_1 => '0',
--	--	SIGNAL_2_BIT_1_2 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_1_2 => '0',
--	--	SIGNAL_2_BIT_1_3 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_1_3 => '0',
--	--	SIGNAL_2_BIT_1_4 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_1_4 => '0',
--	--	SIGNAL_4_BIT_1_1 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_1_1 => '0',
--	--	SIGNAL_4_BIT_1_2 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_1_2 => '0',
--	--	SIGNAL_4_BIT_1_3 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_1_3 => '0',
--	--	SIGNAL_4_BIT_1_4 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_1_4 => '0',
--		SIGNAL_8_BIT_1_1 => S1_1,
--		SIGNAL_8_BIT_SAMPLE_CLK_1_1 => S1_1B_CLK,
--		SIGNAL_8_BIT_1_2 => S1_2,
--		SIGNAL_8_BIT_SAMPLE_CLK_1_2 => S1_2B_CLK,
--		SIGNAL_8_BIT_1_3 => S1_3,
--		SIGNAL_8_BIT_SAMPLE_CLK_1_3 => S1_3B_CLK,
--		SIGNAL_8_BIT_1_4 => S1_4,
--		SIGNAL_8_BIT_SAMPLE_CLK_1_4 => S1_4B_CLK,
--	--	SIGNAL_16_BIT_1_1 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_1_1 => '0',
--	--	SIGNAL_16_BIT_1_2 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_1_2 => '0',
--	--	SIGNAL_16_BIT_1_3 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_1_3 => '0',
--	--	SIGNAL_16_BIT_1_4 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_1_4 => '0',
--		SIGNAL_1_BIT_2_1 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_2_1 => '0',
--		SIGNAL_1_BIT_2_2 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_2_2 => '0',
--		SIGNAL_1_BIT_2_3 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_2_3 => '0',
--		SIGNAL_1_BIT_2_4 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_2_4 => '0',
--	--	SIGNAL_2_BIT_2_1 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_2_1 => '0',
--	--	SIGNAL_2_BIT_2_2 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_2_2 => '0',
--	--	SIGNAL_2_BIT_2_3 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_2_3 => '0',
--	--	SIGNAL_2_BIT_2_4 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_2_4 => '0',
--	--	SIGNAL_4_BIT_2_1 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_2_1 => '0',
--	--	SIGNAL_4_BIT_2_2 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_2_2 => '0',
--	--	SIGNAL_4_BIT_2_3 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_2_3 => '0',
--	--	SIGNAL_4_BIT_2_4 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_2_4 => '0',
--		SIGNAL_8_BIT_2_1 => S2_1,
--		SIGNAL_8_BIT_SAMPLE_CLK_2_1 => S2_1B_CLK,
--		SIGNAL_8_BIT_2_2 => S2_2,
--		SIGNAL_8_BIT_SAMPLE_CLK_2_2 => S2_2B_CLK,
--		SIGNAL_8_BIT_2_3 => S2_3,
--		SIGNAL_8_BIT_SAMPLE_CLK_2_3 => S2_3B_CLK,
--		SIGNAL_8_BIT_2_4 => S2_4,
--		SIGNAL_8_BIT_SAMPLE_CLK_2_4 => S2_4B_CLK,
--	--	SIGNAL_16_BIT_2_1 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_2_1 => '0',
--	--	SIGNAL_16_BIT_2_2 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_2_2 => '0',
--	--	SIGNAL_16_BIT_2_3 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_2_3 => '0',
--	--	SIGNAL_16_BIT_2_4 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_2_4 => '0',
--		SIGNAL_1_BIT_3_1 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_3_1 => '0',
--		SIGNAL_1_BIT_3_2 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_3_2 => '0',
--		SIGNAL_1_BIT_3_3 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_3_3 => '0',
--		SIGNAL_1_BIT_3_4 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_3_4 => '0',
--	--	SIGNAL_2_BIT_3_1 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_3_1 => '0',
--	--	SIGNAL_2_BIT_3_2 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_3_2 => '0',
--	--	SIGNAL_2_BIT_3_3 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_3_3 => '0',
--	--	SIGNAL_2_BIT_3_4 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_3_4 => '0',
--	--	SIGNAL_4_BIT_3_1 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_3_1 => '0',
--	--	SIGNAL_4_BIT_3_2 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_3_2 => '0',
--	--	SIGNAL_4_BIT_3_3 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_3_3 => '0',
--	--	SIGNAL_4_BIT_3_4 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_3_4 => '0',
--		SIGNAL_8_BIT_3_1 => S3_1,
--		SIGNAL_8_BIT_SAMPLE_CLK_3_1 => S3_1B_CLK,
--		SIGNAL_8_BIT_3_2 => S3_2,
--		SIGNAL_8_BIT_SAMPLE_CLK_3_2 => S3_2B_CLK,
--		SIGNAL_8_BIT_3_3 => S3_3,
--		SIGNAL_8_BIT_SAMPLE_CLK_3_3 => S3_3B_CLK,
--		SIGNAL_8_BIT_3_4 => S3_4,
--		SIGNAL_8_BIT_SAMPLE_CLK_3_4 => S3_4B_CLK,
--	--	SIGNAL_16_BIT_3_1 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_3_1 => '0',
--	--	SIGNAL_16_BIT_3_2 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_3_2 => '0',
--	--	SIGNAL_16_BIT_3_3 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_3_3 => '0',
--	--	SIGNAL_16_BIT_3_4 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_3_4 => '0',
--		SIGNAL_1_BIT_4_1 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_4_1 => '0',
--		SIGNAL_1_BIT_4_2 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_4_2 => '0',
--		SIGNAL_1_BIT_4_3 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_4_3 => '0',
--		SIGNAL_1_BIT_4_4 => '0',
--		SIGNAL_1_BIT_SAMPLE_CLK_4_4 => '0',
--	--	SIGNAL_2_BIT_4_1 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_4_1 => '0',
--	--	SIGNAL_2_BIT_4_2 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_4_2 => '0',
--	--	SIGNAL_2_BIT_4_3 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_4_3 => '0',
--	--	SIGNAL_2_BIT_4_4 => (others => '0'),
--	--	SIGNAL_2_BIT_SAMPLE_CLK_4_4 => '0',
--	--	SIGNAL_4_BIT_4_1 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_4_1 => '0',
--	--	SIGNAL_4_BIT_4_2 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_4_2 => '0',
--	--	SIGNAL_4_BIT_4_3 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_4_3 => '0',
--	--	SIGNAL_4_BIT_4_4 => (others => '0'),
--	--	SIGNAL_4_BIT_SAMPLE_CLK_4_4 => '0',
--		SIGNAL_8_BIT_4_1 => S4_1,
--		SIGNAL_8_BIT_SAMPLE_CLK_4_1 => S4_1B_CLK,
--		SIGNAL_8_BIT_4_2 => S4_2,
--		SIGNAL_8_BIT_SAMPLE_CLK_4_2 => S4_2B_CLK,
--		SIGNAL_8_BIT_4_3 => S4_3,
--		SIGNAL_8_BIT_SAMPLE_CLK_4_3 => S4_3B_CLK,
--		SIGNAL_8_BIT_4_4 => S4_4,
--		SIGNAL_8_BIT_SAMPLE_CLK_4_4 => S4_4B_CLK,
--	--	SIGNAL_16_BIT_4_1 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_4_1 => '0',
--	--	SIGNAL_16_BIT_4_2 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_4_2 => '0',
--	--	SIGNAL_16_BIT_4_3 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_4_3 => '0',
--	--	SIGNAL_16_BIT_4_4 => (others => '0'),
--	--	SIGNAL_16_BIT_SAMPLE_CLK_4_4 => '0',
--		TRIGGER_1_BIT_1 => T1,
--		TRIGGER_1_BIT_SAMPLE_CLK_1 => T1_CLK,
--		TRIGGER_1_BIT_2 => T2,
--		TRIGGER_1_BIT_SAMPLE_CLK_2 => T2_CLK,
--		TRIGGER_1_BIT_3 => '0',
--		TRIGGER_1_BIT_SAMPLE_CLK_3 => '0',
--		TRIGGER_1_BIT_4 => '0',
--		TRIGGER_1_BIT_SAMPLE_CLK_4 => '0',
--	--	TRIGGER_2_BIT_1 => (others => '0'),
--	--	TRIGGER_2_BIT_SAMPLE_CLK_1 => '0',
--	--	TRIGGER_2_BIT_2 => (others => '0'),
--	--	TRIGGER_2_BIT_SAMPLE_CLK_2 => '0',
--	--	TRIGGER_2_BIT_3 => (others => '0'),
--	--	TRIGGER_2_BIT_SAMPLE_CLK_3 => '0',
--	--	TRIGGER_2_BIT_4 => (others => '0'),
--	--	TRIGGER_2_BIT_SAMPLE_CLK_4 => '0',
--	--	TRIGGER_4_BIT_1 => (others => '0'),
--	--	TRIGGER_4_BIT_SAMPLE_CLK_1 => '0',
--	--	TRIGGER_4_BIT_2 => (others => '0'),
--	--	TRIGGER_4_BIT_SAMPLE_CLK_2 => '0',
--	--	TRIGGER_4_BIT_3 => (others => '0'),
--	--	TRIGGER_4_BIT_SAMPLE_CLK_3 => '0',
--	--	TRIGGER_4_BIT_4 => (others => '0'),
--	--	TRIGGER_4_BIT_SAMPLE_CLK_4 => '0',
--		TRIGGER_8_BIT_1 => (others => '0'),
--		TRIGGER_8_BIT_SAMPLE_CLK_1 => '0',
--		TRIGGER_8_BIT_2 => (others => '0'),
--		TRIGGER_8_BIT_SAMPLE_CLK_2 => '0',
--		TRIGGER_8_BIT_3 => (others => '0'),
--		TRIGGER_8_BIT_SAMPLE_CLK_3 => '0',
--		TRIGGER_8_BIT_4 => (others => '0'),
--		TRIGGER_8_BIT_SAMPLE_CLK_4 => '0',
--	--	TRIGGER_16_BIT_1 => (others => '0'),
--	--	TRIGGER_16_BIT_SAMPLE_CLK_1 => '0',
--	--	TRIGGER_16_BIT_2 => (others => '0'),
--	--	TRIGGER_16_BIT_SAMPLE_CLK_2 => '0',
--	--	TRIGGER_16_BIT_3 => (others => '0'),
--	--	TRIGGER_16_BIT_SAMPLE_CLK_3 => '0',
--	--	TRIGGER_16_BIT_4 => (others => '0'),
--	--	TRIGGER_16_BIT_SAMPLE_CLK_4 => '0',
--		REG250 => REG250,
--		REG251 => REG251,
--		TRIGGER_REARM_TOGGLE => TRIGGER_REARM_TOGGLE,
--		FORCE_TRIGGER_TOGGLE => FORCE_TRIGGER_TOGGLE,
--		SREG250_READ_TOGGLE => SREG250_READ_TOGGLE,
--		START_CAPTURE_TOGGLE => START_CAPTURE_TOGGLE,
--		TP => open
--	);
--end generate;


--// ARM CO-PROCESSOR INTERFACE ---------------------------------------------------
-- Primarily used for monitoring and control.
-- 8-bit shared address/data bus. clock synchronous.
-- PART OF THE FRAMEWORK. DO NOT CHANGE unless you want to add more control registers 
--(see UC_WRITE_001) or status registers (see UC_READ_001).
-- 
-- Address latch
UC_ADDR_001: process(UC_CSIB_IN, UC_WEBG, UC_ALE_IN, UC_AD)
begin
	if rising_edge(UC_WEBG) then
		if (UC_CSIB_IN = '0') and (UC_ALE_IN = '1') then
			UC_ADDRESS <= unsigned(UC_AD);
	  	end if;
  	end if;
end process;

-- Read status registers 
-- User can define additional control registers using the same pattern. 
UC_READ_001: process(UC_ADDRESS, REG255, RX_LAN, REG251, REG250, SREG)
begin
	case(UC_ADDRESS) is
		-- ComBlock-reserved addresses ----
		when "11111111" => UC_AD_LOCAL <= REG255;		-- reg 255. Async serial from 3 connectors
		when "11111110" => UC_AD_LOCAL <= RX_LAN;-- reg 254 = 8-bit data from LAN M&C channel
		when "11111101" => UC_AD_LOCAL <= REVISION;	-- reg 253 = fpga revision
		when "11111100" => UC_AD_LOCAL <= OPTION;		-- reg 252 = fpga option
		when "11111011" => UC_AD_LOCAL <= REG251;		-- reg 251 =comscope  status
		when "11111010" => UC_AD_LOCAL <= REG250;		-- reg 250 = comscope data byte
		
		-- User-defined status registers -------
		-- SREG0-6 reserved for use by the ARM microcontroller
		when "00000111" => UC_AD_LOCAL <= SREG(7);
		when "00001000" => UC_AD_LOCAL <= SREG(8);
		when "00001001" => UC_AD_LOCAL <= SREG(9);
		when "00001010" => UC_AD_LOCAL <= SREG(10);
		when "00001011" => UC_AD_LOCAL <= SREG(11);
		when "00001100" => UC_AD_LOCAL <= SREG(12);
		when "00001101" => UC_AD_LOCAL <= SREG(13);
		when "00001110" => UC_AD_LOCAL <= SREG(14);
		when "00001111" => UC_AD_LOCAL <= SREG(15);
		when "00010000" => UC_AD_LOCAL <= SREG(16);
		when "00010001" => UC_AD_LOCAL <= SREG(17);
		when "00010010" => UC_AD_LOCAL <= SREG(18);
		when "00010011" => UC_AD_LOCAL <= SREG(19);
		when "00010100" => UC_AD_LOCAL <= SREG(20);
		when "00010101" => UC_AD_LOCAL <= SREG(21);
		when "00010110" => UC_AD_LOCAL <= SREG(22);
		when "00010111" => UC_AD_LOCAL <= SREG(23);
		when "00011000" => UC_AD_LOCAL <= SREG(24);
		when "00011001" => UC_AD_LOCAL <= SREG(25);
		when "00011010" => UC_AD_LOCAL <= SREG(26);
		when "00011011" => UC_AD_LOCAL <= SREG(27);
		when "00011100" => UC_AD_LOCAL <= SREG(28);
		when "00011101" => UC_AD_LOCAL <= SREG(29);
		when "00011110" => UC_AD_LOCAL <= SREG(30);
		when "00011111" => UC_AD_LOCAL <= SREG(31);
		when "00100000" => UC_AD_LOCAL <= SREG(32);
		when "00100001" => UC_AD_LOCAL <= SREG(33);
		when "00100010" => UC_AD_LOCAL <= SREG(34);
		when "00100011" => UC_AD_LOCAL <= SREG(35);
		when "00100100" => UC_AD_LOCAL <= SREG(36);
		when "00100101" => UC_AD_LOCAL <= SREG(37);
		when "00100110" => UC_AD_LOCAL <= SREG(38);
		when "00100111" => UC_AD_LOCAL <= SREG(39);
		when "00101000" => UC_AD_LOCAL <= SREG(40);
		when "00101001" => UC_AD_LOCAL <= SREG(41);
		when "00101010" => UC_AD_LOCAL <= SREG(42);
		when "00101011" => UC_AD_LOCAL <= SREG(43);
		when "00101100" => UC_AD_LOCAL <= SREG(44);
		when "00101101" => UC_AD_LOCAL <= SREG(45);
		
		
		-- user can add more status registers as needed (200+)
		when others => UC_AD_LOCAL <= (others => '0');
	end case;
end process;

UC_AD <= UC_AD_LOCAL when (UC_CSIB_IN = '0') and (UC_REB_IN = '0') else (others => 'Z');
	-- when to drive the data bus between ARM and FPGA
	
-- toggle a few flags upon reading specific status registers
UC_READ_002: process(ASYNC_RESET, UC_REBG, UC_CSIB_IN, UC_ADDRESS, 
						SREG250_READ_TOGGLE, SREG254_READ_TOGGLE)
begin
	if(ASYNC_RESET = '1') then
		SREG250_READ_TOGGLE <= '0';
		SREG254_READ_TOGGLE <= '0';
	elsif rising_edge(UC_REBG) then
		if (UC_CSIB_IN = '0')  then
			if (UC_ADDRESS = 7) then
				SREG7_READ_TOGGLE <= not SREG7_READ_TOGGLE;
			end if;
			if (UC_ADDRESS = 250) then
				SREG250_READ_TOGGLE <= not SREG250_READ_TOGGLE;
			end if;
			if (UC_ADDRESS = 254) then
				SREG254_READ_TOGGLE <= not SREG254_READ_TOGGLE;
			end if;
		end if;
	end if;
end process;

-- reclock with CLK_P
RECLOCK_SREG9_TOGGLE: process(CLK_P,SREG7_READ_TOGGLE)
begin
	if rising_edge(CLK_P) then
		SREG7_READ_TOGGLE_D <= SREG7_READ_TOGGLE;
		SREG7_READ_TOGGLE_D2 <= SREG7_READ_TOGGLE_D;
		if(SREG7_READ_TOGGLE_D /= SREG7_READ_TOGGLE_D2) then
			LATCH_MONITORING_PULSE <= '1';
		else
			LATCH_MONITORING_PULSE <= '0';
		end if;
	end if;
end process;
	
-- write to FPGA control registers
-- Users can define control registers as needed (up to 230) by modifying the UC_WRITE_001 process below.
UC_WRITE_001ax: if (SIMULATION = '0') generate
	UC_WRITE_001a: process(UC_WEBG)
	begin
		if rising_edge(UC_WEBG) then
			if (UC_CSIB_IN = '0') and (UC_ALE_IN = '0') and (UC_REB_IN = '1')  then
				for I in NCREG_IMIN to NCREG_IMAX loop
					if(UC_ADDRESS = I) then
						CREG(I) <= UC_AD;
					end if;
				end loop;
			end if;
		end if;
	end process;

	UC_WRITE_001: process(UC_CSIB_IN, UC_WEBG, UC_ALE_IN, UC_REB_IN, UC_AD)
	begin
		if rising_edge(UC_WEBG) then
			if (UC_CSIB_IN = '0') and (UC_ALE_IN = '0') and (UC_REB_IN = '1')  then

--				if (UC_ADDRESS = NCREG_IMAX) then
-- test test test while testing the DDR3
				if (UC_ADDRESS = 10) or (UC_ADDRESS = NCREG_IMAX) then
					-- dummy write to last control register
					CONFIG_CHANGE_TOGGLE <= not CONFIG_CHANGE_TOGGLE;	
					-- Configuration change toggles upon writing the last control register
					-- This happens invisibly to the user (only the ARM uC writes to this last control register
					-- which is invible to the user and to the ComBlock Control Center).
				end if;
				
				-- Reserved:
				-- REG254 reserved for output serial
				-- REG255 write reserved for output serial (8-bit parallel format)
				if (UC_ADDRESS = 255) then
					-- REG255 write reserved for output serial (8-bit parallel format)
					-- route response to host query over LAN/TCP-IP
					LAN1_TCP_TX_DATA(0) <= UC_AD;
					TX_LAN_TOGGLE <= not TX_LAN_TOGGLE;
				end if;
			end if;
		end if;
	end process;
end generate;


-- initialize control registers for simulation. Ignored at runtime.
UC_WRITE_001y: if (SIMULATION = '1') generate
process
begin
	CREG(0) <= x"00";
	CREG(1) <= x"00";
	CREG(2) <= x"00";
	CREG(3) <= x"00";
	CREG(4) <= x"00";
	CREG(5) <= x"00";
	CREG(6) <= x"01";
	CREG(7) <= x"00";
	CONFIG_CHANGE_TOGGLE <= '0';
	-- etc
	-- start DDR3 test read transaction
	wait for 66us;
	CREG(10) <= x"03";
	CONFIG_CHANGE_TOGGLE <= '1';

	wait for 134us;
	--CREG(10) <= x"03";
	CONFIG_CHANGE_TOGGLE <= '0';

	-- start DDR3 test read transaction
--	wait for 100us;
--	CREG(10) <= x"03";
--	CONFIG_CHANGE_TOGGLE <= '0';
	wait;
end process;
	
end generate;

--// reserved COMSCOPE -------------------------------------------------------
-- Comment out if ComScope feature is unused
UC_WRITE_003: process(UC_CSIB_IN, UC_WEBG, UC_ADDRESS, UC_AD, 
	FORCE_TRIGGER_TOGGLE, TRIGGER_REARM_TOGGLE, START_CAPTURE_TOGGLE)
begin
	if rising_edge(UC_WEBG) then
		if (UC_CSIB_IN = '0') and (UC_ALE_IN = '0') and (UC_REB_IN = '1')  then
			-- Reserved for ComScope			
			if (UC_ADDRESS = 237) then
				REG237 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 238) then
				REG238 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 239) then
				REG239 <= UC_AD;
			end if;
			if (UC_ADDRESS = 240) then
				REG240 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 241) then
				REG241 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 242) then
				REG242 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 243) then
				REG243 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 244) then
				REG244 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 245) then
				REG245 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 246) then
				REG246 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 247) then
				REG247 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 248) then
				REG248 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 249) then
				REG249 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 250) then 
				-- detect one-shot force trigger	
				if(UC_AD(0) = '1') then	
					FORCE_TRIGGER_TOGGLE <= not(FORCE_TRIGGER_TOGGLE);
				end if;	
				-- detect one-shot re-arm	
				if(UC_AD(1) = '1') then	
					TRIGGER_REARM_TOGGLE <= not(TRIGGER_REARM_TOGGLE);
				end if;	
				-- start capturing again
				if(UC_AD(2) = '1') then	
					START_CAPTURE_TOGGLE <= not (START_CAPTURE_TOGGLE);
				end if;	
			end if;
		end if;
	end if;
end process;

--// end of COMSCOPE section -------------------------------------------------------

-- Reclock CONFIG_CHANGE_TOGGLE to be synchronous with processing clock CLK_P
RECLOCK_002: process(CLK_P)
begin
	if rising_edge(CLK_P) then
		CONFIG_CHANGE_TOGGLE_D <= CONFIG_CHANGE_TOGGLE;
		CONFIG_CHANGE_TOGGLE_D2 <= CONFIG_CHANGE_TOGGLE_D;
		if(CONFIG_CHANGE_TOGGLE_D /= CONFIG_CHANGE_TOGGLE_D2) then
			CONFIG_CHANGE_PULSE <= '1';
		else
			CONFIG_CHANGE_PULSE <= '0';
		end if;
	end if;
end process;

-- DNA Port ------------------------------------
-- Read FPGA unique DNA ID
DNA_ID_001: DNA_ID 
	GENERIC MAP(
		CLK_FREQUENCY => 125	-- CLK_P in MHz, as time reference
	)
	PORT MAP(
		CLK => CLK_P,
		SYNC_RESET => SYNC_RESET_CLK_P,
		ID_OUT => DNA_ID_DATA,
		ID_VALID_OUT => open,
		ID_SAMPLE_CLK_OUT => DNA_ID_SAMPLE_CLK 
);


-- M&C USB interface --------------------------
-- REG255 reserved for reading serial port inputs
-- These signals are pulled high (to mimic stop bit).
REG255 <= "1111" & RX_LAN_BUFFER_EMPTY & "111";
	-- M&C port through LAN 
	-- indicates AVAILABILITY of 8-bit byte from LAN. Not actual data.
	-- When low, uC must read byte from LAN

-- Reclock TX_LAN_TOGGLE
RECLOCK_TX_LAN_TOGGLE: process(CLK_P,TX_LAN_TOGGLE)
begin
	if rising_edge(CLK_P) then
		TX_LAN_TOGGLE_D <= TX_LAN_TOGGLE;
		TX_LAN_TOGGLE_D2 <= TX_LAN_TOGGLE_D;
		if(TX_LAN_TOGGLE_D /= TX_LAN_TOGGLE_D2) then
			LAN1_TCP_TX_DATA_VALID(0) <= '1';
		else
			LAN1_TCP_TX_DATA_VALID(0) <= '0';
		end if;
	end if;
end process;

-- Immediately upon completing reading a M&C byte from the USB or LAN, ask for the 
-- next one. 
RECLOCK_RDN_D: process(CLK_P, SREG254_READ_TOGGLE)
begin
	if rising_edge(CLK_P) then
		SREG254_READ_TOGGLE_D <= SREG254_READ_TOGGLE;
		SREG254_READ_TOGGLE_D2 <= SREG254_READ_TOGGLE_D;

		RX_LAN_BUFFER_EMPTY_D <= RX_LAN_BUFFER_EMPTY;
		RX_LAN_BUFFER_EMPTY_D2 <= RX_LAN_BUFFER_EMPTY_D;


		if (SREG254_READ_TOGGLE_D2 /= SREG254_READ_TOGGLE_D) then
			-- end of M&C byte read from ARM uC.
			if(RX_LAN_BUFFER_EMPTY_D2 = '0') then
				-- last M&C byte read was over LAN. Increment LAN elastic buffer read pointer
				RX_LAN_SAMPLE_CLK_REQ <= '1';
					-- identifies LAN as the media through which	this module exchanges 
					-- M&C information. Response will be directed the same way.
			end if;
		else
			RX_LAN_SAMPLE_CLK_REQ <= '0';
		end if;
	end if;
end process;

end Behavioral;
