-------------------------------------------------------------
-- Filename:  COM1600_UDP_TEST.VHD
-- Authors: 
--		Alain Zarembowitch / MSS
-- Version: Rev 1
-- Last modified: 8/9/12
-- Inheritance: COM-1600 template, rev2.
--
-- description:  Test code for COM-5402 IP/TCP/UDP/PING/ARP stack + COM-5401 Tri-mode 10/100/1000 Mbps Ethernet MAC 
-- Two independent IP nodes are instantiated connecting to 2 external PHYs and two IP stacks.
-- The first stack sends PRBS-11 pseudo-random data encapsulated in UDP frames (512 bytes/frame) as fast as possible. 
-- Payload throughput is >878 Mbps over GbE (904 Mbps theoretical, accounting for Ethernet/IP/UDP overhead)
-- The second stack receives the UDP frames and computes the bit error rate. Results are in the form of test points
-- to visualize the valid packets with an oscilloscope.
-- TCP is disabled. 
-- The IP addresses, source and destination addresses are user defined in control registers REG0-REG10.
-- Use the ComBlock control center to change these registers.
-- MAC addresses are fixed within. 
-- 
-- Tested with NTCPSTREAMS, NUDPTX, NUDPRX values in the com5402pkg to 1,1,1 respectively.
--
-- Step1: using the ComBlock Control Center, program the com1600_udp_test.mcs file into the COM1600 FPGA development board
-- Step2: set IP address in control registers 
--   PHY#1 own IP address: REG0 & REG1 & REG2 & REG3
--         sending to: REG5 & REG6 & REG7 & REG8
--   PHY#2 own IP address: REG0 & REG1 & REG2 & REG4
--         sending to: N/A
-- Step3: Using an oscilloscope, verify the following test points on the right connector
--RIGHT_CONNECTOR_A(5 downto 1) <= LAN1_COM5401_TP;
--	-- sending PHY (#1) test points
--	--TP(1) <= MAC_TX_DATA_VALID;	-- tx data from user
--	--TP(2) <= MAC_TX_CTS_local;	-- tx flow control to user
--	--TP(3) <= TX_EVENT1;	-- start tx to PHY
--	--TP(4) <= TX_EVENT2;	-- collision
--	--TP(5) <= TX_EVENT3;	-- done sending frame to PHY
--RIGHT_CONNECTOR_A(10 downto 6) <= LAN2_COM5401_TP;
--	-- receiving PHY (#2) test points
--	--TP(6) <= RX_EVENT1;	-- new packet
--	--TP(7) <= RX_EVENT3;	-- frame delimiter
--	--TP(8) <= RX_EVENT4;	-- valid frame byte
--	--TP(9) <= RX_EVENT5;	-- frame complete
--	--TP(10) <= RX_EVENT5 and not RX_CRC32_VALID;	-- invalid frame CRC
--	
---- received stream information: bad packets, bit error rate
--RIGHT_CONNECTOR_A(11) <= UDP2_RX_DATA_VALID;
--RIGHT_CONNECTOR_A(12) <= UDP2_RX_EOF;
--RIGHT_CONNECTOR_A(13) <= UDP2_BAD_PACKET;
--RIGHT_CONNECTOR_A(14) <= RX_STREAM_DATA_VALID;
--RIGHT_CONNECTOR_A(15) <= BER2_MF_DETECT;
--RIGHT_CONNECTOR_A(16) <= BER2_MF_DETECT_CONFIRMED;
--RIGHT_CONNECTOR_A(17) <= BER2_SYNC_LOCK;
--RIGHT_CONNECTOR_A(18) <= BER2_BYTE_ERROR;
---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.com5402pkg.all;	-- defines global types, number of TCP streams, etc
Library UNISIM;
use UNISIM.vcomponents.all;

entity COM1600_UDP_TEST is
    Port ( 
		--GLOBAL CLOCKS
	   USB_CLK60 : in std_logic;	
			-- 60 MHz reference clock. Generated by the USB PHY on this board.
		EXT_FREQ_REF: in std_logic;
			-- external (higher-stability) frequency reference via J9 SMA connector ("EXT REF")

		--// Left connector, 98 pin PCIe female connector. 
		-- Pins B5,B20,B31,B42 reserved for Ground
		-- Pins A49/B49 reserved for ComBlock Monitoring and Control.
		-- Place B13 in high-impedance when using the 12-bit DAC or vice versa.
		LEFT_CONNECTOR_A: inout std_logic_vector(48 downto 1);
		LEFT_CONNECTOR_B: inout std_logic_vector(48 downto 1);

		--// Right connector: 98 pin PCIe female connector.   
		-- Pins B5,B20,B31,B42 reserved for Ground
		-- Pins A49/B49 reserved for ComBlock Monitoring and Control.
		-- Connector pins A39 - A48, B40,B41,B43-B48 can be used by 
		-- re-routing LEFT_CONNECTOR signals using a resistor array (requires soldering)
		-- See schematics for details.
		RIGHT_CONNECTOR_A: inout std_logic_vector(48 downto 1);
		RIGHT_CONNECTOR_B: inout std_logic_vector(48 downto 1);

		--// Monitoring & Control: ARM Cortex M3 microcontroller interface
		-- asynchronous bus (shared with NAND flash)
		-- set address at the rising edge of UC_WEB_IN when UC_CSIB_IN = '0' and UC_ALE_IN = '1'
		-- write data the rising edge of UC_WEB_IN when UC_CSIB_IN = '0'
		-- read data when  UC_CSIB_IN = '0' and UC_REB_IN = '0'
		UC_CSIB_IN: in std_logic;  -- chip select. active low.
		UC_ALE_IN: in std_logic;  -- address latch enable. active high.
		UC_REB_IN: in std_logic;  -- read enable #
		UC_WEB_IN: in std_logic;	-- write enable #
		UC_AD: inout std_logic_vector(7 downto 0)  -- shared address/data bus

		  
			  );
end entity;

architecture Behavioral of COM1600_UDP_TEST is
--------------------------------------------------------
--      COMPONENTS
--------------------------------------------------------
	COMPONENT CLKGEN_PLL
	PORT(
		CLKREF_IN : IN std_logic;
		CLKOUT0G : OUT std_logic;
		CLKOUT1G : OUT std_logic;
		CLKOUT2G : OUT std_logic;
		LOCKED_PLL : OUT std_logic
		);
	END COMPONENT;

	COMPONENT TIMER_4US
	GENERIC (
		CLK_FREQUENCY: integer 
	);
	PORT(
		ASYNC_RESET : IN std_logic;
		CLK : IN std_logic;          
		TICK_4US : OUT std_logic;
		TICK_100MS: out std_logic
		);
	END COMPONENT;

	COMPONENT COM5401
	GENERIC (
		MII_SEL: std_logic;  
		PHY_ADDR: std_logic_vector(4 downto 0);
		CLK_FREQUENCY: integer;
		SIMULATION: std_logic
	);
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		MAC_TX_CONFIG : IN std_logic_vector(15 downto 0);
		MAC_RX_CONFIG : IN std_logic_vector(15 downto 0);
		MAC_ADDR : IN std_logic_vector(47 downto 0);
		PHY_CONFIG_CHANGE : IN std_logic;
		PHY_RESET : IN std_logic;
		SPEED : IN std_logic_vector(1 downto 0);
		DUPLEX : IN std_logic;
		TEST_MODE : IN std_logic_vector(1 downto 0);
		POWER_DOWN : IN std_logic;
		CLK_SKEW : IN std_logic_vector(15 downto 0);
		MAC_TX_DATA : IN std_logic_vector(7 downto 0);
		MAC_TX_DATA_VALID : IN std_logic;
		MAC_TX_EOF : IN std_logic;
		MAC_RX_CTS : IN std_logic;
		RXC : IN std_logic;
		RXD : IN std_logic_vector(3 downto 0);
		RX_CTL : IN std_logic;
		MII_TX_CLK : IN std_logic;
		GMII_MII_CRS : IN std_logic;
		GMII_MII_COL : IN std_logic;
		GMII_MII_RX_CLK : IN std_logic;
		GMII_MII_RXD : IN std_logic_vector(7 downto 0);
		GMII_MII_RX_DV : IN std_logic;
		GMII_MII_RX_ER : IN std_logic;    
		MDIO : INOUT std_logic;      
		MAC_TX_CTS : OUT std_logic;
		MAC_RX_DATA : OUT std_logic_vector(7 downto 0);
		MAC_RX_DATA_VALID : OUT std_logic;
		MAC_RX_SOF : OUT std_logic;
		MAC_RX_EOF : OUT std_logic;
		TXC : OUT std_logic;
		TXD : OUT std_logic_vector(3 downto 0);
		TX_CTL : OUT std_logic;
		RESET_N : OUT std_logic;
		MCLK : OUT std_logic;
		GMII_TX_CLK : OUT std_logic;
		GMII_MII_TXD : OUT std_logic_vector(7 downto 0);
		GMII_MII_TX_EN : OUT std_logic;
		GMII_MII_TX_ER : OUT std_logic;
		SPEED_STATUS : OUT std_logic_vector(1 downto 0);
		LINK_STATUS : OUT std_logic;
		DUPLEX_STATUS : OUT std_logic;
		PHY_ID : OUT std_logic_vector(15 downto 0);
		N_RX_FRAMES : OUT std_logic_vector(15 downto 0);
		N_RX_BAD_CRCS : OUT std_logic_vector(15 downto 0);
		N_RX_FRAMES_TOO_SHORT : OUT std_logic_vector(15 downto 0);
		N_RX_FRAMES_TOO_LONG : OUT std_logic_vector(15 downto 0);
		N_RX_WRONG_ADDR : OUT std_logic_vector(15 downto 0);
		N_RX_LENGTH_ERRORS : OUT std_logic_vector(15 downto 0);
		CS1 : OUT std_logic_vector(7 downto 0);
		CS1_CLK : OUT std_logic;
		CS2 : OUT std_logic_vector(7 downto 0);
		CS2_CLK : OUT std_logic;
		CS_CLKG : OUT std_logic;
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;

	COMPONENT COM5402
	GENERIC (
		CLK_FREQUENCY: integer;
		SIMULATION: std_logic
	);	
	PORT(
		CLK : IN std_logic;
		ASYNC_RESET : IN std_logic;
		SYNC_RESET : IN std_logic;
		MAC_ADDR : IN std_logic_vector(47 downto 0);
		IPv4_ADDR : IN std_logic_vector(31 downto 0);
		IPv6_ADDR : IN std_logic_vector(127 downto 0);
		SUBNET_MASK: in std_logic_vector(31 downto 0);
		GATEWAY_IP_ADDR: in std_logic_vector(31 downto 0);
		MAC_TX_CTS : IN std_logic;
		MAC_RX_DATA : IN std_logic_vector(7 downto 0);
		MAC_RX_DATA_VALID : IN std_logic;
		MAC_RX_SOF : IN std_logic;
		MAC_RX_EOF : IN std_logic;          
		MAC_TX_DATA : OUT std_logic_vector(7 downto 0);
		MAC_TX_DATA_VALID : OUT std_logic;
		MAC_TX_EOF : OUT std_logic;
		UDP_RX_DATA: out std_logic_vector(7 downto 0);
		UDP_RX_DATA_VALID: out std_logic;
		UDP_RX_SOF: out std_logic;	
		UDP_RX_EOF: out std_logic;	
		UDP_RX_DEST_PORT_NO: in std_logic_vector(15 downto 0);
		UDP_TX_DATA: in std_logic_vector(7 downto 0);
		UDP_TX_DATA_VALID: in std_logic;
		UDP_TX_SOF: in std_logic;	
		UDP_TX_EOF: in std_logic;	
		UDP_TX_CTS: out std_logic;	
		UDP_TX_ACK: out std_logic;	
		UDP_TX_NAK: out std_logic;	
		UDP_TX_DEST_IP_ADDR: in std_logic_vector(127 downto 0);
		UDP_TX_DEST_PORT_NO: in std_logic_vector(15 downto 0);
		UDP_TX_SOURCE_PORT_NO: in std_logic_vector(15 downto 0);
		TCP_RX_DATA: out SLV8xNTCPSTREAMStype;
		TCP_RX_DATA_VALID: out std_logic_vector((NTCPSTREAMS-1) downto 0);
		TCP_RX_RTS: out std_logic;
		TCP_RX_CTS: in std_logic;
		TCP_TX_DATA: in SLV8xNTCPSTREAMStype;
		TCP_TX_DATA_VALID: in std_logic_vector((NTCPSTREAMS-1) downto 0);
		TCP_TX_CTS: out std_logic_vector((NTCPSTREAMS-1) downto 0);	
		CS1 : OUT std_logic_vector(7 downto 0);
		CS1_CLK : OUT std_logic;
		CS2 : OUT std_logic_vector(7 downto 0);
		CS2_CLK : OUT std_logic;
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;

	COMPONENT LFSR11P
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		SAMPLE_CLK_OUT_REQ : IN std_logic;          
		DATA_OUT : OUT std_logic_vector(7 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic;
		SOF_OUT : OUT std_logic
		);
	END COMPONENT;

	COMPONENT STREAM_2_PACKETS
	generic (
		NBUFS: integer;
		SIMULATION: std_logic
	);
	PORT(
		ASYNC_RESET : IN std_logic;
		CLK : IN std_logic;
		TICK_4US : IN std_logic;
		STREAM_DATA : IN std_logic_vector(7 downto 0);
		STREAM_DATA_VALID : IN std_logic;
		CTS_IN : IN std_logic;
		ACK_IN : IN std_logic;
		NAK_IN : IN std_logic;          
		STREAM_CTS : OUT std_logic;
		DATA_OUT : OUT std_logic_vector(7 downto 0);
		DATA_VALID_OUT : OUT std_logic;
		SOF_OUT : OUT std_logic;
		EOF_OUT : OUT std_logic;
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;

	COMPONENT PACKETS_2_STREAM
	generic (
		NBUFS: integer
	);
	PORT(
		ASYNC_RESET : IN std_logic;
		CLK : IN std_logic;
		PACKET_DATA_IN : IN std_logic_vector(7 downto 0);
		PACKET_DATA_VALID_IN : IN std_logic;
		PACKET_EOF_IN : IN std_logic;
		STREAM_CTS_IN : IN std_logic;          
		PACKET_CTS_OUT : OUT std_logic;
		STREAM_DATA_OUT : OUT std_logic_vector(7 downto 0);
		STREAM_DATA_VALID_OUT : OUT std_logic;
		BAD_PACKET : OUT std_logic;
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;

	COMPONENT BER2
	PORT(
		CLK : IN std_logic;
		SYNC_RESET : IN std_logic;
		DATA_IN : IN std_logic_vector(7 downto 0);
		SAMPLE_CLK_IN : IN std_logic;
		CONTROL : IN std_logic_vector(7 downto 0);          
		MF_DETECT : OUT std_logic;
		MF_DETECT_CONFIRMED : OUT std_logic;
		SYNC_LOCK : OUT std_logic;
		BYTE_ERROR : OUT std_logic;
		DATA_REPLICA : OUT std_logic_vector(7 downto 0);
		SAMPLE_CLK_OUT : OUT std_logic;
		BER : OUT std_logic_vector(31 downto 0);
		BER_SAMPLE_CLK : OUT std_logic;
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;

	COMPONENT COMSCOPE
	GENERIC (
		-- select features as needed: number of traces, widths
		-- One must re-synthesize after changing these choices.
		-- enable individual traces. '1' for enable, '0' for disable
		TRACE1_ENABLED: std_logic;	
		TRACE2_ENABLED: std_logic;	
		TRACE3_ENABLED: std_logic;	
		TRACE4_ENABLED: std_logic
	);	
	PORT(
		CLK : IN std_logic;
		ASYNC_RESET : IN std_logic;
		SIGNED_REPRESENTATION_U_SIGNED_N : IN std_logic;
		REG237 : IN std_logic_vector(7 downto 0);
		REG238 : IN std_logic_vector(7 downto 0);
		REG239 : IN std_logic_vector(7 downto 0);
		REG240 : IN std_logic_vector(7 downto 0);
		REG241 : IN std_logic_vector(7 downto 0);
		REG242 : IN std_logic_vector(7 downto 0);
		REG243 : IN std_logic_vector(7 downto 0);
		REG244 : IN std_logic_vector(7 downto 0);
		REG245 : IN std_logic_vector(7 downto 0);
		REG246 : IN std_logic_vector(7 downto 0);
		REG247 : IN std_logic_vector(7 downto 0);
		REG248 : IN std_logic_vector(7 downto 0);
		REG249 : IN std_logic_vector(7 downto 0);
		SIGNAL_1_BIT_1_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_1_BIT_1_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_1_BIT_1_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_1_BIT_1_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_2_BIT_1_1 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_2_BIT_1_2 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_2_BIT_1_3 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_2_BIT_1_4 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_4_BIT_1_1 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_4_BIT_1_2 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_4_BIT_1_3 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_4_BIT_1_4 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_8_BIT_1_1 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_8_BIT_1_2 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_8_BIT_1_3 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_8_BIT_1_4 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_16_BIT_1_1 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_1_1 : IN std_logic;
		SIGNAL_16_BIT_1_2 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_1_2 : IN std_logic;
		SIGNAL_16_BIT_1_3 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_1_3 : IN std_logic;
		SIGNAL_16_BIT_1_4 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_1_4 : IN std_logic;
		SIGNAL_1_BIT_2_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_1_BIT_2_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_1_BIT_2_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_1_BIT_2_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_2_BIT_2_1 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_2_BIT_2_2 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_2_BIT_2_3 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_2_BIT_2_4 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_4_BIT_2_1 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_4_BIT_2_2 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_4_BIT_2_3 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_4_BIT_2_4 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_8_BIT_2_1 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_8_BIT_2_2 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_8_BIT_2_3 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_8_BIT_2_4 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_16_BIT_2_1 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_2_1 : IN std_logic;
		SIGNAL_16_BIT_2_2 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_2_2 : IN std_logic;
		SIGNAL_16_BIT_2_3 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_2_3 : IN std_logic;
		SIGNAL_16_BIT_2_4 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_2_4 : IN std_logic;
		SIGNAL_1_BIT_3_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_1_BIT_3_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_1_BIT_3_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_1_BIT_3_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_2_BIT_3_1 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_2_BIT_3_2 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_2_BIT_3_3 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_2_BIT_3_4 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_4_BIT_3_1 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_4_BIT_3_2 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_4_BIT_3_3 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_4_BIT_3_4 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_8_BIT_3_1 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_8_BIT_3_2 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_8_BIT_3_3 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_8_BIT_3_4 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_16_BIT_3_1 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_3_1 : IN std_logic;
		SIGNAL_16_BIT_3_2 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_3_2 : IN std_logic;
		SIGNAL_16_BIT_3_3 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_3_3 : IN std_logic;
		SIGNAL_16_BIT_3_4 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_3_4 : IN std_logic;
		SIGNAL_1_BIT_4_1 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_1_BIT_4_2 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_1_BIT_4_3 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_1_BIT_4_4 : IN std_logic;
		SIGNAL_1_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		SIGNAL_2_BIT_4_1 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_2_BIT_4_2 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_2_BIT_4_3 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_2_BIT_4_4 : IN std_logic_vector(1 downto 0);
		SIGNAL_2_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		SIGNAL_4_BIT_4_1 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_4_BIT_4_2 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_4_BIT_4_3 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_4_BIT_4_4 : IN std_logic_vector(3 downto 0);
		SIGNAL_4_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		SIGNAL_8_BIT_4_1 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_8_BIT_4_2 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_8_BIT_4_3 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_8_BIT_4_4 : IN std_logic_vector(7 downto 0);
		SIGNAL_8_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		SIGNAL_16_BIT_4_1 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_4_1 : IN std_logic;
		SIGNAL_16_BIT_4_2 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_4_2 : IN std_logic;
		SIGNAL_16_BIT_4_3 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_4_3 : IN std_logic;
		SIGNAL_16_BIT_4_4 : IN std_logic_vector(15 downto 0);
		SIGNAL_16_BIT_SAMPLE_CLK_4_4 : IN std_logic;
		TRIGGER_1_BIT_1 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_1_BIT_2 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_1_BIT_3 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_1_BIT_4 : IN std_logic;
		TRIGGER_1_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_2_BIT_1 : IN std_logic_vector(1 downto 0);
		TRIGGER_2_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_2_BIT_2 : IN std_logic_vector(1 downto 0);
		TRIGGER_2_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_2_BIT_3 : IN std_logic_vector(1 downto 0);
		TRIGGER_2_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_2_BIT_4 : IN std_logic_vector(1 downto 0);
		TRIGGER_2_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_4_BIT_1 : IN std_logic_vector(3 downto 0);
		TRIGGER_4_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_4_BIT_2 : IN std_logic_vector(3 downto 0);
		TRIGGER_4_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_4_BIT_3 : IN std_logic_vector(3 downto 0);
		TRIGGER_4_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_4_BIT_4 : IN std_logic_vector(3 downto 0);
		TRIGGER_4_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_8_BIT_1 : IN std_logic_vector(7 downto 0);
		TRIGGER_8_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_8_BIT_2 : IN std_logic_vector(7 downto 0);
		TRIGGER_8_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_8_BIT_3 : IN std_logic_vector(7 downto 0);
		TRIGGER_8_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_8_BIT_4 : IN std_logic_vector(7 downto 0);
		TRIGGER_8_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_16_BIT_1 : IN std_logic_vector(15 downto 0);
		TRIGGER_16_BIT_SAMPLE_CLK_1 : IN std_logic;
		TRIGGER_16_BIT_2 : IN std_logic_vector(15 downto 0);
		TRIGGER_16_BIT_SAMPLE_CLK_2 : IN std_logic;
		TRIGGER_16_BIT_3 : IN std_logic_vector(15 downto 0);
		TRIGGER_16_BIT_SAMPLE_CLK_3 : IN std_logic;
		TRIGGER_16_BIT_4 : IN std_logic_vector(15 downto 0);
		TRIGGER_16_BIT_SAMPLE_CLK_4 : IN std_logic;
		TRIGGER_REARM_TOGGLE : IN std_logic;
		FORCE_TRIGGER_TOGGLE : IN std_logic;
		SREG250_READ_TOGGLE : IN std_logic;
		START_CAPTURE_TOGGLE : IN std_logic;          
		REG250 : OUT std_logic_vector(7 downto 0);
		REG251 : OUT std_logic_vector(7 downto 0);
		TP : OUT std_logic_vector(10 downto 1)
		);
	END COMPONENT;



--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
-- Suffix _D indicates a one CLK delayed version of the net with the same name
-- Suffix _E indicates a one CLK early version of the net with the same name
-- Suffix _X indicates an extended precision version of the net with the same name
-- Suffix _N indicates an inverted version of the net with the same name
-- CTS = Clear To Send (from receive side for flow control)
-- RTS = Ready To Send 

--// CLOCKS, RESETS
signal CLK_P: std_logic:= '0';
signal USB_CLK60G: std_logic:= '0';
signal LAN1_CLK125: std_logic:= '0';
signal PLL_LOCKED: std_logic:= '0';
signal SYNC_RESET: std_logic := '0';
signal ASYNC_RESET: std_logic:= '0';
signal RESETFLAG_D: std_logic := '0';
signal RESET_STATE: integer range 0 to 3 := 0;
	-- asynchronous reset
signal TICK_4US: std_logic := '0';
signal TICK_100MS: std_logic := '0';


signal RESET_COUNTER: std_logic_vector(23 downto 0) := x"000000";	-- initialize for simulations
	-- spans 2^23/60MHz = 140ms
	
--// USB Interface for M&C
signal SREG254_READ_TOGGLE_D: std_logic:= '0';
signal SREG254_READ_TOGGLE_D2: std_logic:= '0';
signal PHY_VENDOR_ID: std_logic_vector(7 downto 0) := (others => '0');

--// COM-5401 QUAD 10/100/1000 Mbps Ethernet PHYs -------
signal CLK_SKEW: std_logic_vector(15 downto 0) := (others => '0');

signal LAN1_MAC_ADDR: std_logic_vector(47 downto 0) := (others => '0');
signal LAN1_TXC: std_logic:= '0';  -- tx clock
signal LAN1_TXD: std_logic_vector(3 downto 0) := (others => '0');  -- tx data
signal LAN1_TX_CTL: std_logic:= '0';  -- tx control: combines TX_EN and TX_ER
			-- valid at the falling clock edge
signal LAN1_RXC: std_logic:= '0';  -- receive clock
			-- must be delayed by 1.5 to 2.1 ns to prevent glitches
signal LAN1_RXD: std_logic_vector(3 downto 0) := (others => '0');  -- receive data
signal LAN1_RX_CTL: std_logic:= '0';  -- receive control. combines RX_DV and RX_ER
			-- valid at the falling clock edge
			-- Note: Micrel KSZ9021RN PHY defines these as dual-function signals.
			-- Set the strapping options in the .ucf constraint file.
signal LAN1_RESET_N: std_logic:= '0';
			-- PHY reset
signal LAN1_MCLK: std_logic:= '0';
signal LAN1_COM5401_TP: std_logic_vector(10 downto 1);
signal LAN1_PHY_ID: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_MAC_RX_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal LAN1_MAC_RX_DATA_VALID: std_logic:= '0';
signal LAN1_MAC_RX_SOF: std_logic:= '0';
signal LAN1_MAC_RX_EOF: std_logic:= '0';
signal LAN1_MAC_TX_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal LAN1_MAC_TX_DATA_VALID: std_logic:= '0';
signal LAN1_MAC_TX_EOF: std_logic:= '0';
signal LAN1_MAC_TX_CTS: std_logic:= '0';
signal LAN1_LINK_STATUS: std_logic:= '0';
signal LAN1_SPEED_STATUS: std_logic_vector(1 downto 0) := (others => '0');
signal LAN1_DUPLEX_STATUS: std_logic:= '0';
signal LAN1_N_RX_FRAMES: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_N_RX_BAD_CRCS: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_N_RX_FRAMES_TOO_SHORT: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_N_RX_FRAMES_TOO_LONG: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_N_RX_LENGTH_ERRORS: std_logic_vector(15 downto 0) := (others => '0');
signal LAN1_N_RX_WRONG_ADDR: std_logic_vector(15 downto 0) := (others => '0');

signal LAN2_MAC_ADDR: std_logic_vector(47 downto 0) := (others => '0');
signal LAN2_TXC: std_logic:= '0';  -- tx clock
signal LAN2_TXD: std_logic_vector(3 downto 0) := (others => '0');  -- tx data
signal LAN2_TX_CTL: std_logic:= '0';  -- tx control: combines TX_EN and TX_ER
signal LAN2_RXC: std_logic:= '0';  -- receive clock
signal LAN2_RXD: std_logic_vector(3 downto 0) := (others => '0');  -- receive data
signal LAN2_RX_CTL: std_logic:= '0';  -- receive control. combines RX_DV and RX_ER
signal LAN2_RESET_N: std_logic:= '0';
signal LAN2_MCLK: std_logic:= '0';
signal LAN2_PHY_ID: std_logic_vector(15 downto 0) := (others => '0');
signal LAN2_COM5401_TP: std_logic_vector(10 downto 1);
signal LAN2_MAC_RX_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal LAN2_MAC_RX_DATA_VALID: std_logic:= '0';
signal LAN2_MAC_RX_SOF: std_logic:= '0';
signal LAN2_MAC_RX_EOF: std_logic:= '0';
signal LAN2_MAC_TX_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal LAN2_MAC_TX_DATA_VALID: std_logic:= '0';
signal LAN2_MAC_TX_EOF: std_logic:= '0';
signal LAN2_MAC_TX_CTS: std_logic:= '0';
signal LAN2_LINK_STATUS: std_logic:= '0';
signal LAN2_SPEED_STATUS: std_logic_vector(1 downto 0) := (others => '0');
signal LAN2_DUPLEX_STATUS: std_logic:= '0';
signal LAN2_N_RX_FRAMES: std_logic_vector(15 downto 0) := (others => '0');
signal LAN2_N_RX_BAD_CRCS: std_logic_vector(15 downto 0) := (others => '0');
signal LAN2_N_RX_FRAMES_TOO_SHORT: std_logic_vector(15 downto 0) := (others => '0');
signal LAN2_N_RX_FRAMES_TOO_LONG: std_logic_vector(15 downto 0) := (others => '0');
signal LAN2_N_RX_LENGTH_ERRORS: std_logic_vector(15 downto 0) := (others => '0');
signal LAN2_N_RX_WRONG_ADDR: std_logic_vector(15 downto 0) := (others => '0');

--// COM-5402 IP protocols -------
signal COM5402_TP: std_logic_vector(10 downto 1);

signal IP1_ADDRv4: std_logic_vector(31 downto 0) := (others => '0');	
signal UDP1_TX_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal UDP1_TX_DATA_VALID: std_logic := '0';
signal UDP1_TX_SOF: std_logic := '0';	
signal UDP1_TX_EOF: std_logic := '0';	
signal UDP1_TX_CTS: std_logic := '0';	
signal UDP1_TX_ACK: std_logic := '0';	
signal UDP1_TX_NAK: std_logic := '0';	

signal IP2_ADDRv4: std_logic_vector(31 downto 0) := (others => '0');	
signal LAN2_TCP_RX_DATA: SLV8xNTCPSTREAMStype;
signal LAN2_TCP_RX_DATA_VALID: std_logic_vector((NTCPSTREAMS-1) downto 0) := (others => '0');
signal LAN2_TCP_RX_RTS: std_logic:= '0';
signal LAN2_TCP_RX_CTS: std_logic:= '0';
signal LAN2_TCP_TX_DATA: SLV8xNTCPSTREAMStype;
signal LAN2_TCP_TX_DATA_VALID: std_logic_vector((NTCPSTREAMS-1) downto 0) := (others => '0');
signal LAN2_TCP_TX_CTS: std_logic_vector((NTCPSTREAMS-1) downto 0) := (others => '0');
signal UDP2_RX_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal UDP2_RX_DATA_VALID: std_logic := '0';
signal UDP2_RX_EOF: std_logic := '0';	
signal UDP2_BAD_PACKET: std_logic := '0';	

--//-- THROUGHPUT & BER TESTS ----------------------
signal PRBS11_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal PRBS11_DATA_VALID: std_logic := '0';
signal PRBS11_SOF: std_logic := '0';
signal PRBS11_CTS: std_logic := '0';
signal TP_STREAMS2PACKETS: std_logic_vector(10 downto 1) := (others => '0');

signal RX_STREAM_DATA: std_logic_vector(7 downto 0) := (others => '0');
signal RX_STREAM_DATA_VALID: std_logic := '0';

signal BER2_MF_DETECT: std_logic := '0';
signal BER2_MF_DETECT_CONFIRMED: std_logic := '0';
signal BER2_SYNC_LOCK: std_logic := '0';
signal BER2_BYTE_ERROR: std_logic := '0';

-- M&C
signal RX_LAN: std_logic_vector(7 downto 0) := x"00";
signal RX_LAN_RTS: std_logic := '0';
signal RX_LAN_RTS_D: std_logic := '0';
signal RX_LAN_RTS_D2: std_logic := '0';
signal RX_LAN_SAMPLE_CLK_REQ: std_logic := '0';
signal TX_LAN_TOGGLE: std_logic:= '0';
signal TX_LAN_TOGGLE_D: std_logic:= '0';
signal TX_LAN_TOGGLE_D2: std_logic:= '0';
signal TX_LAN: std_logic_vector(7 downto 0) := x"00";
signal TX_LAN_SAMPLE_CLK: std_logic:= '0';


--// ComScope traces
signal CS_CLKG: std_logic:= '0';
signal S1_1: std_logic_vector(7 downto 0) := (others => '0');	
signal S1_1_CLK: std_logic:= '0';
signal S1_1B_CLK: std_logic:= '0';
signal S1_2: std_logic_vector(7 downto 0) := (others => '0');	
signal S1_2_CLK: std_logic:= '0';
signal S1_2B_CLK: std_logic:= '0';
signal S1_3: std_logic_vector(7 downto 0) := (others => '0');	
signal S1_3_CLK: std_logic:= '0';
signal S1_3B_CLK: std_logic:= '0';
signal S1_4: std_logic_vector(7 downto 0) := (others => '0');	
signal S1_4_CLK: std_logic:= '0';
signal S1_4B_CLK: std_logic:= '0';
signal S2_1: std_logic_vector(7 downto 0) := (others => '0');	
signal S2_1_CLK: std_logic:= '0';
signal S2_1B_CLK: std_logic:= '0';
signal S2_2: std_logic_vector(7 downto 0) := (others => '0');	
signal S2_2_CLK: std_logic:= '0';
signal S2_2B_CLK: std_logic:= '0';
signal S2_3: std_logic_vector(7 downto 0) := (others => '0');	
signal S2_3_CLK: std_logic:= '0';
signal S2_3B_CLK: std_logic:= '0';
signal S2_4: std_logic_vector(7 downto 0) := (others => '0');	
signal S2_4_CLK: std_logic:= '0';
signal S2_4B_CLK: std_logic:= '0';
signal S3_1: std_logic_vector(7 downto 0) := (others => '0');	
signal S3_1_CLK: std_logic:= '0';
signal S3_1B_CLK: std_logic:= '0';
signal S3_2: std_logic_vector(7 downto 0) := (others => '0');	
signal S3_2_CLK: std_logic:= '0';
signal S3_2B_CLK: std_logic:= '0';
signal S3_3: std_logic_vector(7 downto 0) := (others => '0');	
signal S3_3_CLK: std_logic:= '0';
signal S3_3B_CLK: std_logic:= '0';
signal S3_4: std_logic_vector(7 downto 0) := (others => '0');	
signal S3_4_CLK: std_logic:= '0';
signal S3_4B_CLK: std_logic:= '0';

signal T1: std_logic:= '0';
signal T1_CLK: std_logic:= '0';
signal T2: std_logic:= '0';
signal T2_CLK: std_logic:= '0';

signal TRIGGER_REARM_TOGGLE: std_logic:= '0';
signal FORCE_TRIGGER_TOGGLE: std_logic:= '0';
signal START_CAPTURE_TOGGLE: std_logic:= '0';
signal SREG250_READ_TOGGLE: std_logic:= '0';

--// ARM co-processor interface
signal UC_WEBG: std_logic:= '0';  -- WE# through global buffer
signal UC_ADDRESS: std_logic_vector(7 downto 0) := (others => '0');
signal UC_AD_LOCAL: std_logic_vector(7 downto 0) := (others => '0');
signal UC_RDN_D: std_logic:= '0';
signal UC_RDN_D2: std_logic:= '0';
signal CONFIG_CHANGE_TOGGLE: std_logic:= '0';
signal CONFIG_CHANGE_TOGGLE_D: std_logic:= '0';
signal CONFIG_CHANGE_TOGGLE_D2: std_logic:= '0';
signal CONFIG_CHANGE_PULSE: std_logic:= '0';

--// Control Registers
signal REG0: std_logic_vector(7 downto 0) :=  x"AC";	-- LAN1 IP address
signal REG1: std_logic_vector(7 downto 0) :=  x"10";
signal REG2: std_logic_vector(7 downto 0) :=  x"01";
signal REG3: std_logic_vector(7 downto 0) :=  x"81";
signal REG4: std_logic_vector(7 downto 0) :=  x"2C";	-- last byte of LAN2
signal REG5: std_logic_vector(7 downto 0) :=  x"AC";	-- UDP dest address
signal REG6: std_logic_vector(7 downto 0) :=  x"10";
signal REG7: std_logic_vector(7 downto 0) :=  x"01";
signal REG8: std_logic_vector(7 downto 0) :=  x"2C";
signal REG9: std_logic_vector(7 downto 0) := (others => '0');
signal REG10: std_logic_vector(7 downto 0) := (others => '0');
signal REG11: std_logic_vector(7 downto 0) := (others => '0');
signal REG12: std_logic_vector(7 downto 0) := (others => '0');
signal REG13: std_logic_vector(7 downto 0) := (others => '0');
signal REG14: std_logic_vector(7 downto 0) := (others => '0');
signal REG255: std_logic_vector(7 downto 0) := (others => '0');

--// Status Registers
signal SREG0: std_logic_vector(7 downto 0) := (others => '0');
signal SREG1: std_logic_vector(7 downto 0) := (others => '0');
signal SREG2: std_logic_vector(7 downto 0) := (others => '0');
signal SREG3: std_logic_vector(7 downto 0) := (others => '0');
signal SREG4: std_logic_vector(7 downto 0) := (others => '0');
signal SREG5: std_logic_vector(7 downto 0) := (others => '0');
signal SREG6: std_logic_vector(7 downto 0) := (others => '0');
signal SREG7: std_logic_vector(7 downto 0) := (others => '0');
signal SREG8: std_logic_vector(7 downto 0) := (others => '0');
signal SREG9: std_logic_vector(7 downto 0) := (others => '0');
signal SREG254_READ_TOGGLE: std_logic:= '0';			

--// ComScope control registers
signal REG237: std_logic_vector(7 downto 0):= "00000000";
signal REG238: std_logic_vector(7 downto 0):= "00000000";
signal REG239: std_logic_vector(7 downto 0):= "00000000";
signal REG240: std_logic_vector(7 downto 0):= "00001101";	-- Trace 1 signal selection
signal REG241: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG242: std_logic_vector(7 downto 0):= "00001110";	-- Trace 2 signal selection
signal REG243: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG244: std_logic_vector(7 downto 0):= "00000000";	-- Trace 3 signal selection
signal REG245: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG246: std_logic_vector(7 downto 0):= "00000000";	-- Trace 4 signal selection
signal REG247: std_logic_vector(7 downto 0):= "00000000";	-- Trigger position, decimation
signal REG248: std_logic_vector(7 downto 0):= "10001101";	-- Trigger edge, trigger signal
signal REG249: std_logic_vector(7 downto 0):= "10111111";	-- Trigger threshold
signal REG250: std_logic_vector(7 downto 0):= "00000000";
signal REG251: std_logic_vector(7 downto 0):= "00000000";


--// FPGA option and revision (ASCII format)
-- These two ASCII characters appear in the Comblock Control Center.
-- Very helpful in identifying which firmware version is currently running
-- in the FPGA. 
-- '0' = 48
-- 'A' = 65
constant OPTION: std_logic_vector(7 downto 0) := x"20";	-- '-'
constant REVISION: std_logic_vector(7 downto 0) := x"31";	-- '1'
constant SIMULATION: std_logic := '0';	-- '1' during simulation for shorter reset. MUST be reset to '0' prior to synthesis.
--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
begin
--// CLOCKS, RESET ---------------------
-- Generate miscellaneous global clocks and resets from the 
-- reference 60 MHz clock (from the USB PHY). 
-- FOR MOST APPLICATIONS, KEEP THIS SECTION UNCHANGED.
-- Most Common changes: change the various system clock frequencies within CLKGEN_PLL 

-- Generate miscellaneous global clocks and resets from the 
-- reference 60 MHz clock (from the USB PHY). 
RESET_STATE_MACHINE_001: process(USB_CLK60G)
begin
	if rising_edge(USB_CLK60G) then
		-- PLL need time to lock. The reset of the application is still in reset
		if(RESET_COUNTER(17) = '0') and (SIMULATION = '0') then
			-- wait a bit before asserting the PLL lock
			RESET_COUNTER <= RESET_COUNTER + 1;
		elsif(RESET_COUNTER(5) = '0') and (SIMULATION = '1') then  
			-- make it short during simulations
			-- wait a bit before asserting the PLL lock
			RESET_COUNTER <= RESET_COUNTER + 1;
		elsif(PLL_LOCKED = '1') then
			-- assert the PLL lock
			RESET_STATE <= 1;
		end if;
	end if;
end process;

ASYNC_RESET <= '0' when (RESET_STATE = 1) else '1';

-- convert ASYNC_RESET to a CLK-synchronous RESET pulse
RESET_002: process(ASYNC_RESET, CLK_P)
begin	
	if rising_edge(CLK_P) then
		RESETFLAG_D <= ASYNC_RESET;
		SYNC_RESET <= RESETFLAG_D;
	end if;
end process;

-- force selection of correct IBUF

BUFG_006: BUFG  port map (I=> UC_WEB_IN, O=> UC_WEBG);	
	-- ARM WE#

CLKGEN_PLL_001: CLKGEN_PLL PORT MAP(
	CLKREF_IN => USB_CLK60,
	CLKOUT0G => USB_CLK60G,		-- USB clock, global
	CLKOUT1G => CLK_P,			-- processing clock, global
	CLKOUT2G => open,				-- unused
	LOCKED_PLL => PLL_LOCKED
);

TIMER_4US_001: TIMER_4US 
GENERIC MAP(
	CLK_FREQUENCY => 125		-- in MHz, as time reference
)
PORT MAP(
	ASYNC_RESET => ASYNC_RESET,
	CLK => CLK_P,
	TICK_4US => TICK_4US,
	TICK_100MS => TICK_100MS
);


--// COM-5401 QUAD 10/100/1000 Mbps Ethernet PHYs -------
CLK_SKEW <= x"B7F7";  -- delay TXC/RXC 

-- PHY #1
LAN1_MAC_ADDR <= x"000102030405";	-- natural order, just like reading the address from left to right.
LAN1_RXC <= LEFT_CONNECTOR_A(1);
LAN1_RX_CTL <= LEFT_CONNECTOR_A(2);
LAN1_RXD(3 downto 0) <= LEFT_CONNECTOR_A(6 downto 3);
LEFT_CONNECTOR_A(6 downto 1) <=  (others => 'Z');	-- Input-only: make sure that out is tri-stated.
LEFT_CONNECTOR_A(7) <= LAN1_TXC;
LEFT_CONNECTOR_A(8) <= LAN1_TX_CTL;
LEFT_CONNECTOR_A(12 downto 9) <= LAN1_TXD(3 downto 0); 
--LAN1_CLK125 <= LEFT_CONNECTOR_A(13);	-- 125 MHz reference frequency from PHY #1 (unused, disabled in .ucf)
LEFT_CONNECTOR_A(14 downto 13) <= (others => 'Z');	-- Input-only: make sure that out is tri-stated.
LEFT_CONNECTOR_A(15) <= LAN1_RESET_N;
LEFT_CONNECTOR_A(16) <= LAN1_MCLK;

-- PHY #2
LAN2_MAC_ADDR <= x"000102030406";	-- natural order, just like reading the address from left to right.
LAN2_RXC <= LEFT_CONNECTOR_B(1);
LAN2_RX_CTL <= LEFT_CONNECTOR_B(2);
LAN2_RXD(1 downto 0) <= LEFT_CONNECTOR_B(4 downto 3);
LAN2_RXD(3 downto 2) <= LEFT_CONNECTOR_B(7 downto 6);
LEFT_CONNECTOR_B(7 downto 1) <=  (others => 'Z');	-- Input-only: make sure that out is tri-stated.
LEFT_CONNECTOR_B(8) <= LAN2_TXC;
LEFT_CONNECTOR_B(9) <= LAN2_TX_CTL;
LEFT_CONNECTOR_B(13 downto 10) <= LAN2_TXD(3 downto 0); 
LEFT_CONNECTOR_B(15 downto 14) <= (others => 'Z');	-- Input-only: make sure that out is tri-stated.
LEFT_CONNECTOR_B(16) <= LAN2_RESET_N;
LEFT_CONNECTOR_B(17) <= LAN2_MCLK;

---- PHY #3
--LAN3_RXC <= LEFT_CONNECTOR_A(19);
--LAN3_RX_CTL <= LEFT_CONNECTOR_A(20);
--LAN3_RXD(3 downto 0) <= LEFT_CONNECTOR_A(24 downto 21);
--LEFT_CONNECTOR_A(26 downto 19) <=  (others => 'Z');	-- Input-only: make sure that out is tri-stated.
--LEFT_CONNECTOR_A(25) <= LAN3_TXC;
--LEFT_CONNECTOR_A(26) <= LAN3_TX_CTL;
--LEFT_CONNECTOR_A(30 downto 27) <= LAN3_TXD(3 downto 0); 
--LEFT_CONNECTOR_A(32 downto 31) <= (others => 'Z');	-- Input-only: make sure that out is tri-stated.
--LEFT_CONNECTOR_A(33) <= LAN3_RESET_N;
--LEFT_CONNECTOR_A(34) <= LAN3_MCLK;
--
---- PHY #4
--LAN4_RXC <= LEFT_CONNECTOR_B(21);
--LAN4_RX_CTL <= LEFT_CONNECTOR_B(22);
--LAN4_RXD(3 downto 0) <= LEFT_CONNECTOR_B(26 downto 23);
--LEFT_CONNECTOR_B(26 downto 21) <=  (others => 'Z');	-- Input-only: make sure that out is tri-stated.
--LEFT_CONNECTOR_B(27) <= LAN4_TXC;
--LEFT_CONNECTOR_B(28) <= LAN4_TX_CTL;
--LEFT_CONNECTOR_B(30 downto 29) <= LAN4_TXD(1 downto 0); 
--LEFT_CONNECTOR_B(33 downto 32) <= LAN4_TXD(3 downto 2); 
--LEFT_CONNECTOR_B(35 downto 34) <= (others => 'Z');	-- Input-only: make sure that out is tri-stated.
--LEFT_CONNECTOR_B(36) <= LAN4_RESET_N;
--LEFT_CONNECTOR_B(37) <= LAN4_MCLK;


LAN_001: COM5401 
GENERIC MAP(
	MII_SEL => '0',   	-- select which MII interface: 0 = RGMII, 1 = GMII/MII
	PHY_ADDR => "00100",	-- PHY_AD0/1 pulled-down by 1KOhm, PHY_AD2 pulled-up in .ucf file.
	CLK_FREQUENCY => 125,
	SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK_P,
	SYNC_RESET => SYNC_RESET,
	MAC_TX_CONFIG => X"0003",	-- MAC must must provide pad + crc32
	MAC_RX_CONFIG => x"000F",	-- promiscuous mode, strip crc32, accept broadcast/multicast
	MAC_ADDR => LAN1_MAC_ADDR,
	PHY_CONFIG_CHANGE => CONFIG_CHANGE_PULSE,	
	PHY_RESET => '0',
	SPEED => "11",	-- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	DUPLEX => '1',	-- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	TEST_MODE => "00",	-- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	POWER_DOWN => '0', -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	CLK_SKEW => CLK_SKEW, -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	MAC_TX_DATA => LAN1_MAC_TX_DATA,
	MAC_TX_DATA_VALID => LAN1_MAC_TX_DATA_VALID,
	MAC_TX_EOF => LAN1_MAC_TX_EOF,
	MAC_TX_CTS => LAN1_MAC_TX_CTS,
	MAC_RX_DATA => LAN1_MAC_RX_DATA,	
	MAC_RX_DATA_VALID => LAN1_MAC_RX_DATA_VALID,
	MAC_RX_SOF => LAN1_MAC_RX_SOF,
	MAC_RX_EOF => LAN1_MAC_RX_EOF,
	MAC_RX_CTS => '1',  -- follow-on processing is expected to always accept data even at max speed.
	-- RGMII interface ----------------
	TXC => LAN1_TXC,	
	TXD => LAN1_TXD,
	TX_CTL => LAN1_TX_CTL,
	RXC => LAN1_RXC,
	RXD => LAN1_RXD,
	RX_CTL => LAN1_RX_CTL,
	RESET_N => LAN1_RESET_N,
	MCLK => LAN1_MCLK,
	MDIO => LEFT_CONNECTOR_A(17),	-- PHY#1
--	MDIO => LEFT_CONNECTOR_B(18),	-- PHY#2
--	MDIO => LEFT_CONNECTOR_A(35),	-- PHY#3
--	MDIO => LEFT_CONNECTOR_B(38),	-- PHY#4
	-- end of RGMII interface --------
	MII_TX_CLK => '0',	-- MII interface is unused -----
	GMII_TX_CLK => open,
	GMII_MII_TXD => open,
	GMII_MII_TX_EN => open,
	GMII_MII_TX_ER => open,
	GMII_MII_CRS => '0',
	GMII_MII_COL => '0',
	GMII_MII_RX_CLK => '0',
	GMII_MII_RXD => x"00",
	GMII_MII_RX_DV => '0',
	GMII_MII_RX_ER => '0',  -- end of MII interface ------
	LINK_STATUS => LAN1_LINK_STATUS,
	SPEED_STATUS => LAN1_SPEED_STATUS,
	DUPLEX_STATUS => LAN1_DUPLEX_STATUS,
	PHY_ID => LAN1_PHY_ID,
	N_RX_FRAMES => LAN1_N_RX_FRAMES,
	N_RX_BAD_CRCS => LAN1_N_RX_BAD_CRCS,
	N_RX_FRAMES_TOO_SHORT => LAN1_N_RX_FRAMES_TOO_SHORT,
	N_RX_FRAMES_TOO_LONG => LAN1_N_RX_FRAMES_TOO_LONG,
	N_RX_WRONG_ADDR => LAN1_N_RX_WRONG_ADDR,
	N_RX_LENGTH_ERRORS => LAN1_N_RX_LENGTH_ERRORS,
	CS_CLKG => open,
	CS1 => open,
	CS1_CLK => open,
	CS2 => open,
	CS2_CLK => open,
	TP => LAN1_COM5401_TP
);

-- hardware test: read PHY_ID
--SREG8 <= LAN1_PHY_ID(7 downto 0);
--SREG9 <= LAN1_PHY_ID(15 downto 8);

LAN_002: COM5401 
GENERIC MAP(
	MII_SEL => '0',   	-- select which MII interface: 0 = RGMII, 1 = GMII/MII
	PHY_ADDR => "00100",	-- PHY_AD0/1 pulled-down by 1KOhm, PHY_AD2 pulled-up in .ucf file.
	CLK_FREQUENCY => 125,
	SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK_P,
	SYNC_RESET => SYNC_RESET,
	MAC_TX_CONFIG => X"0003",	-- MAC must must provide pad + crc32
	MAC_RX_CONFIG => x"000F",	-- promiscuous mode, strip crc32, accept broadcast/multicast
	MAC_ADDR => LAN2_MAC_ADDR,
	PHY_CONFIG_CHANGE => CONFIG_CHANGE_PULSE,	
	PHY_RESET => '0',
	SPEED => "11",	-- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	DUPLEX => '1',	-- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	TEST_MODE => "00",	-- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	POWER_DOWN => '0', -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	CLK_SKEW => CLK_SKEW, -- supersedes defaults within if PHY_CONFIG_CHANGE = '1'
	MAC_TX_DATA => LAN2_MAC_TX_DATA,
	MAC_TX_DATA_VALID => LAN2_MAC_TX_DATA_VALID,
	MAC_TX_EOF => LAN2_MAC_TX_EOF,
	MAC_TX_CTS => LAN2_MAC_TX_CTS,
	MAC_RX_DATA => LAN2_MAC_RX_DATA,	
	MAC_RX_DATA_VALID => LAN2_MAC_RX_DATA_VALID,
	MAC_RX_SOF => LAN2_MAC_RX_SOF,
	MAC_RX_EOF => LAN2_MAC_RX_EOF,
	MAC_RX_CTS => '1',  -- follow-on processing is expected to always accept data even at max speed.
	-- RGMII interface ----------------
	TXC => LAN2_TXC,	
	TXD => LAN2_TXD,
	TX_CTL => LAN2_TX_CTL,
	RXC => LAN2_RXC,
	RXD => LAN2_RXD,
	RX_CTL => LAN2_RX_CTL,
	RESET_N => LAN2_RESET_N,
	MCLK => LAN2_MCLK,
--	MDIO => LEFT_CONNECTOR_A(17),	-- PHY#1
	MDIO => LEFT_CONNECTOR_B(18),	-- PHY#2
--	MDIO => LEFT_CONNECTOR_A(35),	-- PHY#3
--	MDIO => LEFT_CONNECTOR_B(38),	-- PHY#4
	-- end of RGMII interface --------
	MII_TX_CLK => '0',	-- MII interface is unused -----
	GMII_TX_CLK => open,
	GMII_MII_TXD => open,
	GMII_MII_TX_EN => open,
	GMII_MII_TX_ER => open,
	GMII_MII_CRS => '0',
	GMII_MII_COL => '0',
	GMII_MII_RX_CLK => '0',
	GMII_MII_RXD => x"00",
	GMII_MII_RX_DV => '0',
	GMII_MII_RX_ER => '0',  -- end of MII interface ------
	LINK_STATUS => LAN2_LINK_STATUS,
	SPEED_STATUS => LAN2_SPEED_STATUS,
	DUPLEX_STATUS => LAN2_DUPLEX_STATUS,
	PHY_ID => LAN2_PHY_ID,
	N_RX_FRAMES => LAN2_N_RX_FRAMES,
	N_RX_BAD_CRCS => LAN2_N_RX_BAD_CRCS,
	N_RX_FRAMES_TOO_SHORT => LAN2_N_RX_FRAMES_TOO_SHORT,
	N_RX_FRAMES_TOO_LONG => LAN2_N_RX_FRAMES_TOO_LONG,
	N_RX_WRONG_ADDR => LAN2_N_RX_WRONG_ADDR,
	N_RX_LENGTH_ERRORS => LAN2_N_RX_LENGTH_ERRORS,
	CS_CLKG => open,
	CS1 => open,
	CS1_CLK => open,
	CS2 => open,
	CS2_CLK => open,
	TP => LAN2_COM5401_TP
);

-- hardware test: read PHY_ID
SREG8 <= LAN2_PHY_ID(7 downto 0);
SREG9 <= LAN2_PHY_ID(15 downto 8);

--// COM-5402 IP protocols -------

-- CONNECTED TO PHY #1
IP1_ADDRv4(31 downto 0) <= REG0 & REG1 & REG2 & REG3;

IPSTACK_001: COM5402 
GENERIC MAP(
		CLK_FREQUENCY => 125,	-- in MHz, as time reference
		SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK_P,
	ASYNC_RESET => ASYNC_RESET,	-- to be progressively phased out. Replace with SYNC_RESET
	SYNC_RESET => SYNC_RESET,
	MAC_ADDR => LAN1_MAC_ADDR,
	IPv4_ADDR => IP1_ADDRv4,
	IPv6_ADDR => x"00000000000000000000000000000000",
	SUBNET_MASK => x"FFFFFF00",
	GATEWAY_IP_ADDR => x"AC100103",
	-- MAC interface
	MAC_TX_DATA => LAN1_MAC_TX_DATA,
	MAC_TX_DATA_VALID => LAN1_MAC_TX_DATA_VALID,
	MAC_TX_EOF => LAN1_MAC_TX_EOF,
	MAC_TX_CTS => LAN1_MAC_TX_CTS,
	MAC_RX_DATA => LAN1_MAC_RX_DATA,
	MAC_RX_DATA_VALID => LAN1_MAC_RX_DATA_VALID,
	MAC_RX_SOF => LAN1_MAC_RX_SOF,
	MAC_RX_EOF => LAN1_MAC_RX_EOF,
	 -- UDP rx
	 UDP_RX_DATA => open,
	 UDP_RX_DATA_VALID => open,
	 UDP_RX_SOF => open,
	 UDP_RX_EOF => open,
	 UDP_RX_DEST_PORT_NO => x"1234",
	-- UDP tx
	UDP_TX_DATA => UDP1_TX_DATA,
	UDP_TX_DATA_VALID => UDP1_TX_DATA_VALID,
	UDP_TX_SOF => UDP1_TX_SOF,
	UDP_TX_EOF => UDP1_TX_EOF,
	UDP_TX_CTS => UDP1_TX_CTS,
	UDP_TX_ACK => UDP1_TX_ACK,
	UDP_TX_NAK => UDP1_TX_NAK,
	UDP_TX_DEST_IP_ADDR => x"000000000000000000000000" & REG5 & REG6 & REG7 & REG8,
	UDP_TX_DEST_PORT_NO => x"1234",
	UDP_TX_SOURCE_PORT_NO => x"5678",
	-- TCP rx streams
	TCP_RX_DATA => open,
	TCP_RX_DATA_VALID => open,
	TCP_RX_RTS => open,
	TCP_RX_CTS => '0',
	-- TCP tx streams
	TCP_TX_DATA => (others => (others => '0')),
	TCP_TX_DATA_VALID => (others => '0'),	
	TCP_TX_CTS => open,
	-- Monitoring
	CS1 => S1_1,
	CS1_CLK => S1_1_CLK,
	CS2 => S2_1,
	CS2_CLK => S2_1_CLK,
	TP => COM5402_TP	
);


-- CONNECTED TO PHY #2
IP2_ADDRv4(31 downto 0) <= REG0 & REG1 & REG2 & REG4;

IPSTACK_002: COM5402 
GENERIC MAP(
		CLK_FREQUENCY => 125,	-- in MHz, as time reference
		SIMULATION => SIMULATION
)
PORT MAP(
	CLK => CLK_P,
	ASYNC_RESET => ASYNC_RESET,	-- to be progressively phased out. Replace with SYNC_RESET
	SYNC_RESET => SYNC_RESET,
	MAC_ADDR => LAN2_MAC_ADDR,
	IPv4_ADDR => IP2_ADDRv4,
	IPv6_ADDR => x"00000000000000000000000000000000",
	SUBNET_MASK => x"FFFFFF00",
	GATEWAY_IP_ADDR => x"AC100103",
	-- MAC interface
	MAC_TX_DATA => LAN2_MAC_TX_DATA,
	MAC_TX_DATA_VALID => LAN2_MAC_TX_DATA_VALID,
	MAC_TX_EOF => LAN2_MAC_TX_EOF,
	MAC_TX_CTS => LAN2_MAC_TX_CTS,
	MAC_RX_DATA => LAN2_MAC_RX_DATA,
	MAC_RX_DATA_VALID => LAN2_MAC_RX_DATA_VALID,
	MAC_RX_SOF => LAN2_MAC_RX_SOF,
	MAC_RX_EOF => LAN2_MAC_RX_EOF,
	-- UDP rx
	UDP_RX_DATA => UDP2_RX_DATA,
	UDP_RX_DATA_VALID => UDP2_RX_DATA_VALID,
	UDP_RX_SOF => open,
	UDP_RX_EOF => UDP2_RX_EOF,
	UDP_RX_DEST_PORT_NO => x"1234",
	-- UDP tx
	UDP_TX_DATA => x"00",
	UDP_TX_DATA_VALID => '0',
	UDP_TX_SOF => '0',
	UDP_TX_EOF => '0',
	UDP_TX_CTS => open,
	UDP_TX_ACK => open,
	UDP_TX_NAK => open,
	UDP_TX_DEST_IP_ADDR => x"000000000000000000000000" & REG9 & REG10 & REG11 & REG12,
	UDP_TX_DEST_PORT_NO => x"1234",
	UDP_TX_SOURCE_PORT_NO => x"5678",
	-- TCP rx streams
	TCP_RX_DATA => open,
	TCP_RX_DATA_VALID => open,
	TCP_RX_RTS => open,
	TCP_RX_CTS => '0',
	-- TCP tx streams
	TCP_TX_DATA => (others => (others => '0')),
	TCP_TX_DATA_VALID => (others => '0'),	
	TCP_TX_CTS => open,
	-- Monitoring
	CS1 => open,
	CS1_CLK => open,
	CS2 => open,
	CS2_CLK => open,
	TP => open	
);


--//-- THROUGHPUT & BER TESTS ----------------------
-- Generate a pseudo-random binary sequence PRBS11 (to compute BER at the receiving end)
LFSR11P_001: LFSR11P PORT MAP(
	CLK => CLK_P,
	SYNC_RESET => ASYNC_RESET,
	DATA_OUT => PRBS11_DATA,
	SAMPLE_CLK_OUT => PRBS11_DATA_VALID,
	SOF_OUT => PRBS11_SOF,
	SAMPLE_CLK_OUT_REQ => PRBS11_CTS
);
	
-- segment data stream into packets 
STREAM_2_PACKETS_001: STREAM_2_PACKETS 
GENERIC MAP(
	NBUFS => 1,
	SIMULATION => SIMULATION
)
PORT MAP(
	ASYNC_RESET => ASYNC_RESET,
	CLK => CLK_P,
	TICK_4US => TICK_4US,
	STREAM_DATA => PRBS11_DATA,
	STREAM_DATA_VALID => PRBS11_DATA_VALID,
	STREAM_CTS => PRBS11_CTS,
	DATA_OUT => UDP1_TX_DATA,
	DATA_VALID_OUT => UDP1_TX_DATA_VALID,
	SOF_OUT => UDP1_TX_SOF,
	EOF_OUT => UDP1_TX_EOF,
	CTS_IN => UDP1_TX_CTS,
	ACK_IN => UDP1_TX_ACK,
	NAK_IN => UDP1_TX_NAK,
	TP => TP_STREAMS2PACKETS
);


-- packets to data stream
PACKETS_2_STREAM_001: PACKETS_2_STREAM 
GENERIC MAP(
	NBUFS => 1
)
PORT MAP(
	ASYNC_RESET => ASYNC_RESET,
	CLK => CLK_P,
	PACKET_DATA_IN => UDP2_RX_DATA,
	PACKET_DATA_VALID_IN => UDP2_RX_DATA_VALID,
	PACKET_EOF_IN => UDP2_RX_EOF,
	PACKET_CTS_OUT => open,
	STREAM_DATA_OUT => RX_STREAM_DATA,
	STREAM_DATA_VALID_OUT => RX_STREAM_DATA_VALID,
	STREAM_CTS_IN => '1',
	BAD_PACKET => UDP2_BAD_PACKET,
	TP => open
);

-- detect errors
BER2_001: BER2 PORT MAP(
	CLK => CLK_P,
	SYNC_RESET => ASYNC_RESET,
	DATA_IN => RX_STREAM_DATA,
	SAMPLE_CLK_IN => RX_STREAM_DATA_VALID,
	CONTROL => x"03",	-- 1 million bit window
	MF_DETECT => BER2_MF_DETECT,
	MF_DETECT_CONFIRMED => BER2_MF_DETECT_CONFIRMED,
	SYNC_LOCK => BER2_SYNC_LOCK,
	BYTE_ERROR => BER2_BYTE_ERROR,
	DATA_REPLICA => open,
	SAMPLE_CLK_OUT => open,
	BER => open,
	BER_SAMPLE_CLK => open,
	TP => open
);



	
	
--
---- test code to send a UDP frame packet once every ... 
--UDP_TX_testsim: process(CLK_P)
--begin
--	if rising_edge(CLK_P) then
--		if(UDP1_TX_CTS_B = '1') then
--			if(TICK_100MS = '1') then	-- 100 ms tick
--				UDP1_TX_DATA_VALID <= '1';
--				UDP1_TX_SOF <= '1';
--				UDP1_TX_EOF <= '0';
--				UDP1_TX_DATA <= x"00";
--			elsif(UDP1_TX_DATA > x"F0") then
--				-- end of udp frame
--				UDP1_TX_EOF <= '0';
--				UDP1_TX_DATA_VALID <= '0';
--			else
--				UDP1_TX_DATA <= UDP1_TX_DATA + 1;
--				UDP1_TX_SOF <= '0';
--				if(UDP1_TX_DATA = x"F0") then
--					UDP1_TX_EOF <= '1';
--				else
--					UDP1_TX_EOF <= '0';
--				end if;
--			end if;
--		else
--			UDP1_TX_DATA_VALID <= '0';
--			UDP1_TX_SOF <= '0';
--			UDP1_TX_EOF <= '0';
--		end if;
--	end if;
--end process;
--

--// TEST POINTS (debugging)
--RIGHT_CONNECTOR_A(1) <= LAN2_MAC_RX_DATA_VALID;
--RIGHT_CONNECTOR_A(2) <= LAN2_MAC_RX_SOF;
--RIGHT_CONNECTOR_A(3) <= LAN2_MAC_RX_EOF;
--RIGHT_CONNECTOR_A(4) <= UDP1_TX_DATA_VALID;
--RIGHT_CONNECTOR_A(5) <= UDP1_TX_CTS;
--RIGHT_CONNECTOR_A(6) <= UDP1_TX_SOF;
--RIGHT_CONNECTOR_A(7) <= UDP1_TX_EOF;
--RIGHT_CONNECTOR_A(8) <= UDP1_TX_ACK;
--RIGHT_CONNECTOR_A(9) <= UDP1_TX_NAK;
--RIGHT_CONNECTOR_A(10) <= '1' when UDP2_RX_EOF = '1' and UDP2_RX_DATA_VALID = '0'  else '0';

RIGHT_CONNECTOR_A(5 downto 1) <= LAN1_COM5401_TP(5 downto 1);
	-- sending PHY (#1) test points
	--TP(1) <= MAC_TX_DATA_VALID;	-- tx data from user
	--TP(2) <= MAC_TX_CTS_local;	-- tx flow control to user
	--TP(3) <= TX_EVENT1;	-- start tx to PHY
	--TP(4) <= TX_EVENT2;	-- collision
	--TP(5) <= TX_EVENT3;	-- done sending frame to PHY
RIGHT_CONNECTOR_A(10 downto 6) <= LAN2_COM5401_TP(10 downto 6);
	-- receiving PHY (#2) test points
	--TP(6) <= RX_EVENT1;	-- new packet
	--TP(7) <= RX_EVENT3;	-- frame delimiter
	--TP(8) <= RX_EVENT4;	-- valid frame byte
	--TP(9) <= RX_EVENT5;	-- frame complete
	--TP(10) <= RX_EVENT5 and not RX_CRC32_VALID;	-- invalid frame CRC
	
RIGHT_CONNECTOR_A(11) <= UDP2_RX_DATA_VALID;
RIGHT_CONNECTOR_A(12) <= UDP2_RX_EOF;
RIGHT_CONNECTOR_A(13) <= UDP2_BAD_PACKET;
RIGHT_CONNECTOR_A(14) <= RX_STREAM_DATA_VALID;
RIGHT_CONNECTOR_A(15) <= BER2_MF_DETECT;
RIGHT_CONNECTOR_A(16) <= BER2_MF_DETECT_CONFIRMED;
RIGHT_CONNECTOR_A(17) <= BER2_SYNC_LOCK;
RIGHT_CONNECTOR_A(18) <= BER2_BYTE_ERROR;

-- MAC/PHY status
--RIGHT_CONNECTOR_A(1) <= LAN1_LINK_STATUS;
--RIGHT_CONNECTOR_A(2) <= LAN1_DUPLEX_STATUS;
--RIGHT_CONNECTOR_A(3) <= LAN1_SPEED_STATUS(0);
--RIGHT_CONNECTOR_A(4) <= LAN1_SPEED_STATUS(1);
--RIGHT_CONNECTOR_A(5) <= LAN2_LINK_STATUS;
--RIGHT_CONNECTOR_A(6) <= LAN2_DUPLEX_STATUS;
--RIGHT_CONNECTOR_A(7) <= LAN2_SPEED_STATUS(0);
--RIGHT_CONNECTOR_A(8) <= LAN2_SPEED_STATUS(1);



--// COMSCOPE -----------------------------------------------------
--  Comment in/out as needed 
-- 
-- Define Comscope traces here 
-- Trace 1
--S1_1 <= see COM-5401
S1_2 <= LAN1_MAC_TX_DATA_VALID & "0000000";
S1_2_CLK <= '1';

-- Trace 2
--S2_1 <= see COM-5401
--S2_1_CLK <=

-- Trace 3
--S3_1 <= COM3504_AUXADC1_DOUT(11 downto 4);
--S3_1_CLK <= '1';

-- Trigger (1-bit format, undefine
T1 <= LAN1_MAC_TX_DATA_VALID;
T1_CLK <= '1';

S1_1B_CLK <= S1_1_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
S1_2B_CLK <= S1_2_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
S1_3B_CLK <= S1_3_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock
S1_4B_CLK <= S1_4_CLK or REG240(7);	-- Nominal sampling clock or real-time processing clock

S2_1B_CLK <= S2_1_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
S2_2B_CLK <= S2_2_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
S2_3B_CLK <= S2_3_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock
S2_4B_CLK <= S2_4_CLK or REG242(7);	-- Nominal sampling clock or real-time processing clock

S3_1B_CLK <= S3_1_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
S3_2B_CLK <= S3_2_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
S3_3B_CLK <= S3_3_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock
S3_4B_CLK <= S3_4_CLK or REG244(7);	-- Nominal sampling clock or real-time processing clock


COMSCOPE_001: COMSCOPE 
generic map(
	TRACE1_ENABLED => '1',
	TRACE2_ENABLED => '1',
	TRACE3_ENABLED => '0',
	TRACE4_ENABLED => '0'
)
port map(
   CLK => CLK_P,
	ASYNC_RESET => ASYNC_RESET,
	SIGNED_REPRESENTATION_U_SIGNED_N => REG248(6),	-- trigger format signed(1) or unsigned(0)
	REG237 => REG237,
	REG238 => REG238,
	REG239 => REG239,
	REG240 => REG240,
	REG241 => REG241,
	REG242 => REG242,
	REG243 => REG243,
	REG244 => REG244,
	REG245 => REG245,
	REG246 => REG246,
	REG247 => REG247,
	REG248 => REG248,
	REG249 => REG249,
	SIGNAL_1_BIT_1_1 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_1_1 => '0',
	SIGNAL_1_BIT_1_2 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_1_2 => '0',
	SIGNAL_1_BIT_1_3 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_1_3 => '0',
	SIGNAL_1_BIT_1_4 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_1_4 => '0',
	SIGNAL_2_BIT_1_1 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_1_1 => '0',
	SIGNAL_2_BIT_1_2 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_1_2 => '0',
	SIGNAL_2_BIT_1_3 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_1_3 => '0',
	SIGNAL_2_BIT_1_4 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_1_4 => '0',
	SIGNAL_4_BIT_1_1 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_1_1 => '0',
	SIGNAL_4_BIT_1_2 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_1_2 => '0',
	SIGNAL_4_BIT_1_3 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_1_3 => '0',
	SIGNAL_4_BIT_1_4 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_1_4 => '0',
	SIGNAL_8_BIT_1_1 => S1_1,
	SIGNAL_8_BIT_SAMPLE_CLK_1_1 => S1_1B_CLK,
	SIGNAL_8_BIT_1_2 => S1_2,
	SIGNAL_8_BIT_SAMPLE_CLK_1_2 => S1_2B_CLK,
	SIGNAL_8_BIT_1_3 => S1_3,
	SIGNAL_8_BIT_SAMPLE_CLK_1_3 => S1_3B_CLK,
	SIGNAL_8_BIT_1_4 => S1_4,
	SIGNAL_8_BIT_SAMPLE_CLK_1_4 => S1_4B_CLK,
	SIGNAL_16_BIT_1_1 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_1_1 => '0',
	SIGNAL_16_BIT_1_2 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_1_2 => '0',
	SIGNAL_16_BIT_1_3 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_1_3 => '0',
	SIGNAL_16_BIT_1_4 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_1_4 => '0',
	SIGNAL_1_BIT_2_1 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_2_1 => '0',
	SIGNAL_1_BIT_2_2 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_2_2 => '0',
	SIGNAL_1_BIT_2_3 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_2_3 => '0',
	SIGNAL_1_BIT_2_4 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_2_4 => '0',
	SIGNAL_2_BIT_2_1 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_2_1 => '0',
	SIGNAL_2_BIT_2_2 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_2_2 => '0',
	SIGNAL_2_BIT_2_3 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_2_3 => '0',
	SIGNAL_2_BIT_2_4 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_2_4 => '0',
	SIGNAL_4_BIT_2_1 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_2_1 => '0',
	SIGNAL_4_BIT_2_2 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_2_2 => '0',
	SIGNAL_4_BIT_2_3 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_2_3 => '0',
	SIGNAL_4_BIT_2_4 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_2_4 => '0',
	SIGNAL_8_BIT_2_1 => S2_1,
	SIGNAL_8_BIT_SAMPLE_CLK_2_1 => S2_1B_CLK,
	SIGNAL_8_BIT_2_2 => S2_2,
	SIGNAL_8_BIT_SAMPLE_CLK_2_2 => S2_2B_CLK,
	SIGNAL_8_BIT_2_3 => S2_3,
	SIGNAL_8_BIT_SAMPLE_CLK_2_3 => S2_3B_CLK,
	SIGNAL_8_BIT_2_4 => S2_4,
	SIGNAL_8_BIT_SAMPLE_CLK_2_4 => S2_4B_CLK,
	SIGNAL_16_BIT_2_1 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_2_1 => '0',
	SIGNAL_16_BIT_2_2 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_2_2 => '0',
	SIGNAL_16_BIT_2_3 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_2_3 => '0',
	SIGNAL_16_BIT_2_4 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_2_4 => '0',
	SIGNAL_1_BIT_3_1 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_3_1 => '0',
	SIGNAL_1_BIT_3_2 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_1_BIT_3_3 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_1_BIT_3_4 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_2_BIT_3_1 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_3_1 => '0',
	SIGNAL_2_BIT_3_2 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_2_BIT_3_3 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_2_BIT_3_4 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_4_BIT_3_1 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_3_1 => '0',
	SIGNAL_4_BIT_3_2 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_4_BIT_3_3 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_4_BIT_3_4 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_8_BIT_3_1 => S3_1,
	SIGNAL_8_BIT_SAMPLE_CLK_3_1 => S3_1B_CLK,
	SIGNAL_8_BIT_3_2 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_8_BIT_3_3 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_8_BIT_3_4 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_16_BIT_3_1 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_3_1 => '0',
	SIGNAL_16_BIT_3_2 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_3_2 => '0',
	SIGNAL_16_BIT_3_3 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_3_3 => '0',
	SIGNAL_16_BIT_3_4 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_3_4 => '0',
	SIGNAL_1_BIT_4_1 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_1_BIT_4_2 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_1_BIT_4_3 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_1_BIT_4_4 => '0',
	SIGNAL_1_BIT_SAMPLE_CLK_4_4 => '0',
	SIGNAL_2_BIT_4_1 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_2_BIT_4_2 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_2_BIT_4_3 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_2_BIT_4_4 => (others => '0'),
	SIGNAL_2_BIT_SAMPLE_CLK_4_4 => '0',
	SIGNAL_4_BIT_4_1 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_4_BIT_4_2 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_4_BIT_4_3 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_4_BIT_4_4 => (others => '0'),
	SIGNAL_4_BIT_SAMPLE_CLK_4_4 => '0',
	SIGNAL_8_BIT_4_1 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_8_BIT_4_2 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_8_BIT_4_3 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_8_BIT_4_4 => (others => '0'),
	SIGNAL_8_BIT_SAMPLE_CLK_4_4 => '0',
	SIGNAL_16_BIT_4_1 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_4_1 => '0',
	SIGNAL_16_BIT_4_2 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_4_2 => '0',
	SIGNAL_16_BIT_4_3 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_4_3 => '0',
	SIGNAL_16_BIT_4_4 => (others => '0'),
	SIGNAL_16_BIT_SAMPLE_CLK_4_4 => '0',
	TRIGGER_1_BIT_1 => T1,
	TRIGGER_1_BIT_SAMPLE_CLK_1 => T1_CLK,
	TRIGGER_1_BIT_2 => T2,
	TRIGGER_1_BIT_SAMPLE_CLK_2 => T2_CLK,
	TRIGGER_1_BIT_3 => '0',
	TRIGGER_1_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_1_BIT_4 => '0',
	TRIGGER_1_BIT_SAMPLE_CLK_4 => '0',
	TRIGGER_2_BIT_1 => (others => '0'),
	TRIGGER_2_BIT_SAMPLE_CLK_1 => '0',
	TRIGGER_2_BIT_2 => (others => '0'),
	TRIGGER_2_BIT_SAMPLE_CLK_2 => '0',
	TRIGGER_2_BIT_3 => (others => '0'),
	TRIGGER_2_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_2_BIT_4 => (others => '0'),
	TRIGGER_2_BIT_SAMPLE_CLK_4 => '0',
	TRIGGER_4_BIT_1 => (others => '0'),
	TRIGGER_4_BIT_SAMPLE_CLK_1 => '0',
	TRIGGER_4_BIT_2 => (others => '0'),
	TRIGGER_4_BIT_SAMPLE_CLK_2 => '0',
	TRIGGER_4_BIT_3 => (others => '0'),
	TRIGGER_4_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_4_BIT_4 => (others => '0'),
	TRIGGER_4_BIT_SAMPLE_CLK_4 => '0',
	TRIGGER_8_BIT_1 => (others => '0'),
	TRIGGER_8_BIT_SAMPLE_CLK_1 => '0',
	TRIGGER_8_BIT_2 => (others => '0'),
	TRIGGER_8_BIT_SAMPLE_CLK_2 => '0',
	TRIGGER_8_BIT_3 => (others => '0'),
	TRIGGER_8_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_8_BIT_4 => (others => '0'),
	TRIGGER_8_BIT_SAMPLE_CLK_4 => '0',
	TRIGGER_16_BIT_1 => (others => '0'),
	TRIGGER_16_BIT_SAMPLE_CLK_1 => '0',
	TRIGGER_16_BIT_2 => (others => '0'),
	TRIGGER_16_BIT_SAMPLE_CLK_2 => '0',
	TRIGGER_16_BIT_3 => (others => '0'),
	TRIGGER_16_BIT_SAMPLE_CLK_3 => '0',
	TRIGGER_16_BIT_4 => (others => '0'),
	TRIGGER_16_BIT_SAMPLE_CLK_4 => '0',
	REG250 => REG250,
	REG251 => REG251,
	TRIGGER_REARM_TOGGLE => TRIGGER_REARM_TOGGLE,
	FORCE_TRIGGER_TOGGLE => FORCE_TRIGGER_TOGGLE,
	SREG250_READ_TOGGLE => SREG250_READ_TOGGLE,
	START_CAPTURE_TOGGLE => START_CAPTURE_TOGGLE,
	TP => open
);



--// ARM CO-PROCESSOR INTERFACE ---------------------------------------------------
-- Primarily used for monitoring and control.
-- 8-bit shared address/data bus. clock synchronous.
-- PART OF THE FRAMEWORK. DO NOT CHANGE unless you want to 
-- add more control registers (see UC_WRITE_001) or status registers (see UC_READ_001).
-- 
-- Address latch
UC_ADDR_001: process(UC_CSIB_IN, UC_WEBG, UC_ALE_IN, UC_AD)
begin
	if rising_edge(UC_WEBG) then
		if (UC_CSIB_IN = '0') and (UC_ALE_IN = '1') then
			UC_ADDRESS <= UC_AD;
	  	end if;
  	end if;
end process;

-- Read status registers 
-- This template defines 10 status registers. 
-- User can define additional control registers using the same pattern. 
UC_READ_001: process(UC_ADDRESS, REG255, REG251, REG250, PHY_VENDOR_ID,
	SREG0, SREG1, SREG2, SREG3, SREG4, SREG5, SREG6, SREG7, SREG8, SREG9)
begin
	case(UC_ADDRESS) is
		-- ComBlock-reserved addresses ----
		when "11111111" => UC_AD_LOCAL <= REG255;		-- reg 255. Async serial from 3 connectors
		when "11111110" => UC_AD_LOCAL <= RX_LAN;		-- reg 254 = 8-bit data from LAN M&C channel
		when "11111101" => UC_AD_LOCAL <= REVISION;	-- reg 253 = fpga revision
		when "11111100" => UC_AD_LOCAL <= OPTION;		-- reg 252 = fpga option
		when "11111011" => UC_AD_LOCAL <= REG251;		-- reg 251 =comscope  status
		when "11111010" => UC_AD_LOCAL <= REG250;		-- reg 250 = comscope data byte
		
		-- User-defined status registers -------
		when "00000000" => UC_AD_LOCAL <= SREG0;
		when "00000001" => UC_AD_LOCAL <= SREG1;
		when "00000010" => UC_AD_LOCAL <= SREG2;
		when "00000011" => UC_AD_LOCAL <= SREG3;
		when "00000100" => UC_AD_LOCAL <= SREG4;
		when "00000101" => UC_AD_LOCAL <= SREG5;
		when "00000110" => UC_AD_LOCAL <= SREG6;
		when "00000111" => UC_AD_LOCAL <= PHY_VENDOR_ID;
		when "00001000" => UC_AD_LOCAL <= SREG8;
		when "00001001" => UC_AD_LOCAL <= SREG9;
		
		
		-- user can add more status registers as needed (200+)
		when others => UC_AD_LOCAL <= (others => '0');
	end case;
end process;

UC_AD <= UC_AD_LOCAL when (UC_CSIB_IN = '0') and (UC_REB_IN = '0') else (others => 'Z');
	-- when to drive the data bus between ARM and FPGA
	
-- toggle a few flags upon reading specific status registers
UC_READ_002: process(ASYNC_RESET, UC_REB_IN, UC_CSIB_IN, UC_ADDRESS, 
						SREG250_READ_TOGGLE, SREG254_READ_TOGGLE)
begin
	if(ASYNC_RESET = '1') then
		SREG250_READ_TOGGLE <= '0';
		SREG254_READ_TOGGLE <= '0';
	elsif rising_edge(UC_REB_IN) then
		if (UC_CSIB_IN = '0')  then
			if (UC_ADDRESS = 250) then
				SREG250_READ_TOGGLE <= not SREG250_READ_TOGGLE;
			end if;
			if (UC_ADDRESS = 254) then
				SREG254_READ_TOGGLE <= not SREG254_READ_TOGGLE;
			end if;
		end if;
	end if;
end process;
			
	
-- write to FPGA control registers
-- This template defines 10 control registers. 
-- User can define additional control registers using the same pattern. 
UC_WRITE_001: process(UC_CSIB_IN, UC_WEBG, UC_ALE_IN, UC_REB_IN, UC_AD)
begin
	if rising_edge(UC_WEBG) then
		if (UC_CSIB_IN = '0') and (UC_ALE_IN = '0') and (UC_REB_IN = '1')  then
			if (UC_ADDRESS = 0) then
				REG0 <= UC_AD;
			end if;
			if (UC_ADDRESS = 1) then
				REG1 <= UC_AD;
			end if;
			if (UC_ADDRESS = 2) then
				REG2 <= UC_AD;
			end if;
			if (UC_ADDRESS = 3) then
				REG3 <= UC_AD;
			end if;
			if (UC_ADDRESS = 4) then
				REG4 <= UC_AD;
			end if;
			if (UC_ADDRESS = 5) then
				REG5 <= UC_AD;
			end if;
			if (UC_ADDRESS = 6) then
				REG6 <= UC_AD;
			end if;
			if (UC_ADDRESS = 7) then
				REG7 <= UC_AD;
			end if;
			if (UC_ADDRESS = 8) then
				REG8 <= UC_AD;
			end if;
			if (UC_ADDRESS = 9) then
				REG9 <= UC_AD;
			end if;
			if (UC_ADDRESS = 10) then
				REG10 <= UC_AD;
			end if;
			if (UC_ADDRESS = 11) then
				REG11 <= UC_AD;
			end if;
			if (UC_ADDRESS = 12) then
				REG12 <= UC_AD;
			end if;
			if (UC_ADDRESS = 13) then
				REG13 <= UC_AD;
			end if;
			if (UC_ADDRESS = 14) then
				REG14 <= UC_AD;
				CONFIG_CHANGE_TOGGLE <= not CONFIG_CHANGE_TOGGLE;	
				-- Configuration change toggles upon writing the last control register
			end if;
			-- user can add more control registers as needed (200+)



			-- Reserved:
			-- REG254 reserved for output serial
			if (UC_ADDRESS = 255) then
				-- REG255 write reserved for output serial (8-bit parallel format)
				-- route response to host query over LAN 
				TX_LAN <= UC_AD;
				TX_LAN_TOGGLE <= not TX_LAN_TOGGLE;
			end if;
		end if;
	end if;
end process;

--// reserved COMSCOPE -------------------------------------------------------
-- Comment out if ComScope feature is unused
UC_WRITE_002: process(UC_CSIB_IN, UC_WEBG, UC_ADDRESS, UC_AD, 
	FORCE_TRIGGER_TOGGLE, TRIGGER_REARM_TOGGLE, START_CAPTURE_TOGGLE)
begin
	if rising_edge(UC_WEBG) then
		if (UC_CSIB_IN = '0') and (UC_ALE_IN = '0') and (UC_REB_IN = '1')  then
			-- Reserved for ComScope			
			if (UC_ADDRESS = 237) then
				REG237 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 238) then
				REG238 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 239) then
				REG239 <= UC_AD;
			end if;
			if (UC_ADDRESS = 240) then
				REG240 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 241) then
				REG241 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 242) then
				REG242 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 243) then
				REG243 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 244) then
				REG244 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 245) then
				REG245 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 246) then
				REG246 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 247) then
				REG247 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 248) then
				REG248 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 249) then
				REG249 <= UC_AD;	
			end if;
			if (UC_ADDRESS = 250) then 
				-- detect one-shot force trigger	
				if(UC_AD(0) = '1') then	
					FORCE_TRIGGER_TOGGLE <= not(FORCE_TRIGGER_TOGGLE);
				end if;	
				-- detect one-shot re-arm	
				if(UC_AD(1) = '1') then	
					TRIGGER_REARM_TOGGLE <= not(TRIGGER_REARM_TOGGLE);
				end if;	
				-- start capturing again
				if(UC_AD(2) = '1') then	
					START_CAPTURE_TOGGLE <= not (START_CAPTURE_TOGGLE);
				end if;	
			end if;
		end if;
	end if;
end process;

--// end of COMSCOPE section -------------------------------------------------------

-- Reclock CONFIG_CHANGE_TOGGLE to be synchronous with processing clock CLK_P
RECLOCK_002: process(CLK_P)
begin
	if rising_edge(CLK_P) then
		CONFIG_CHANGE_TOGGLE_D <= CONFIG_CHANGE_TOGGLE;
		CONFIG_CHANGE_TOGGLE_D2 <= CONFIG_CHANGE_TOGGLE_D;
		if(CONFIG_CHANGE_TOGGLE_D /= CONFIG_CHANGE_TOGGLE_D2) then
			CONFIG_CHANGE_PULSE <= '1';
		else
			CONFIG_CHANGE_PULSE <= '0';
		end if;
	end if;
end process;


-- M&C LAN interface --------------------------
-- REG255 reserved for reading serial port inputs
-- These signals are pulled high (to mimic stop bit).
REG255(2 downto 0) <= "111";
REG255(3) <= not RX_LAN_RTS; 	
	-- indicates AVAILABILITY of 8-bit byte from LAN. Not actual data.
	-- When low, uC must read byte from LAN. 
REG255(7 downto 4) <= "1111";


-- Reclock TX_LAN_TOGGLE
RECLOCK_TX_LAN_TOGGLE: process(CLK_P,TX_LAN_TOGGLE)
begin
	if rising_edge(CLK_P) then
		TX_LAN_TOGGLE_D <= TX_LAN_TOGGLE;
		TX_LAN_TOGGLE_D2 <= TX_LAN_TOGGLE_D;
		if(TX_LAN_TOGGLE_D /= TX_LAN_TOGGLE_D2) then
				-- identifies LAN as the media through which	this module exchanges 
				-- M&C information. Response will be directed the same way.
			TX_LAN_SAMPLE_CLK <= '1';
			TX_LAN <= X"00";	-- TODO
		else
			TX_LAN_SAMPLE_CLK <= '0';
		end if;
	end if;
end process;

-- Immediately upon completing reading a byte from the LAN, ask for the 
-- next one. 
-- RACE CONDITION??????? ARM IS FAST!!!!
RECLOCK_RDN_D: process(CLK_P, SREG254_READ_TOGGLE)
begin
	if rising_edge(CLK_P) then
		SREG254_READ_TOGGLE_D <= SREG254_READ_TOGGLE;
		SREG254_READ_TOGGLE_D2 <= SREG254_READ_TOGGLE_D;

		RX_LAN_RTS_D <= RX_LAN_RTS;
		RX_LAN_RTS_D2 <= RX_LAN_RTS_D;

		if (SREG254_READ_TOGGLE_D2 /= SREG254_READ_TOGGLE_D) then
			-- end of M&C byte read from ARM uC.
			if(RX_LAN_RTS_D2 = '1') then
				-- last M&C byte read was over LAN. Increment LAN elastic buffer read pointer
				RX_LAN_SAMPLE_CLK_REQ <= '1';
			end if;
		else
			RX_LAN_SAMPLE_CLK_REQ <= '0';
		end if;
	end if;
end process;


end Behavioral;
