--------------------------------------------------------------------------------
-- Company: MSS/ComBlock
-- Engineer: Alain Zarembowitch
--
-- Create Date:   10:56:17 03/04/2010
-- Design Name:   
-- Module Name:   C:/Users/Admin/Documents/VHDL source/com-5401/sim/tbMII_MI.vhd
-- Project Name:  com-5401
-- Target Device:  Spartan-6 LX16
-- Tool versions:  ISE 11.4
-- Description: Simulation of the MDIO interface. A write transaction is followed by a 
-- read transaction.  
-- 
-- VHDL Test Bench Created by ISE for module: MII_MI
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tbMII_MI IS
END tbMII_MI;
 
ARCHITECTURE behavior OF tbMII_MI IS 
 
--------------------------------------------------------
--      COMPONENTS
--------------------------------------------------------
	COMPONENT MII_MI
	GENERIC (
		PHY_ADDR: std_logic_vector(4 downto 0)
	);	
	PORT(
		SYNC_RESET : IN std_logic;
		CLK : IN std_logic;
		MI_REGAD : IN std_logic_vector(4 downto 0);
		MI_TX_DATA : IN std_logic_vector(15 downto 0);
		MI_READ_START : IN std_logic;
		MI_WRITE_START : IN std_logic;    
		MDIO : INOUT std_logic;      
		MI_RX_DATA : OUT std_logic_vector(15 downto 0);
		MI_TRANSACTION_COMPLETE : OUT std_logic;
		MCLK : OUT std_logic
		);
	END COMPONENT;
 
    

   --Inputs
   signal SYNC_RESET : std_logic := '0';
   signal CLK : std_logic := '0';
   signal MI_REGAD : std_logic_vector(4 downto 0) := (others => '0');
   signal MI_TX_DATA : std_logic_vector(15 downto 0) := (others => '0');
   signal MI_READ_START : std_logic := '0';
   signal MI_WRITE_START : std_logic := '0';
 
	--BiDirs
   signal MDIO : std_logic;

 	--Outputs
   signal MI_RX_DATA : std_logic_vector(15 downto 0);
   signal MI_TRANSACTION_COMPLETE : std_logic;
   signal MCLK : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 8 ns;
--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
Inst_MII_MI: MII_MI 
GENERIC MAP(
	PHY_ADDR => "00100"
)
PORT MAP(
	SYNC_RESET => SYNC_RESET,
	CLK => CLK,
	MI_REGAD => MI_REGAD,
	MI_TX_DATA => MI_TX_DATA,
	MI_RX_DATA => MI_RX_DATA,
	MI_READ_START => MI_READ_START,
	MI_WRITE_START => MI_WRITE_START,
	MI_TRANSACTION_COMPLETE => MI_TRANSACTION_COMPLETE,
	MCLK => MCLK,
	MDIO => MDIO
);

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 
	MI_REGAD <= "01010";
	MI_TX_DATA <= x"A50F";
	SYNC_RESET <= '0';
	
   -- Stimulus process
   write_proc: process
   begin		
		MI_WRITE_START <= '0';
      wait for 100 ns;	
		MI_WRITE_START <= '1';
		wait for 10 ns;
		MI_WRITE_START <= '0';
	   wait;
   end process;


  read_proc: process
   begin		
		MI_READ_START <= '0';
      wait for 34000 ns;	
		MI_READ_START <= '1';
		wait for 10 ns;
		MI_READ_START <= '0';
	   wait;
   end process;
	

  mdio_data: process
   begin		
		MDIO <= 'Z';
      wait for 52600 ns;	
		MDIO <= '0';
      wait for 400 ns;	
		MDIO <= '1';
      wait for 3000 ns;	
		MDIO <= '0';
	   wait;
   end process;
	
END;
