for hardware target: COM-1800 R2
Support for 1GbE tested
DDR3 controller generated by Xilinx MIG 7 series V2.3. Tested with Vivado only. Not compatible with ISE.
Verified data integrity through DDR3 at 666.66 MSamples/s (333.33 MHz)

-- Remaining issue  10/13/15 
-- doubt about the DDR3 wrapper... need a bit more testing
In particular, some read samples seem to be missing (flow control?)
Data integrity is good though.
For example: if start address = 0, ceiling address = 0x00010000, then
DDR3_RD_ADDR ends at 0000FF88 instead of 0000FFF8
Maybe a misunderstanding of the MIG signals? refresh cycle every 1us or so?

Configured for testing this case further (current .bit file)
1. set start address REG0,1,2,3
2. set ceiling address REG4,5,6,7
3. trigger a read cycle  @001SRG1003
4. force terminate a read cycle @001SRG1004
4. check DDR3_RD_ADDR in status registers 
	SREG(10) <= std_logic_vector(DDR3_RD_ADDR(31 downto 24));
	SREG(11) <= std_logic_vector(DDR3_RD_ADDR(23 downto 16));
	SREG(12) <= std_logic_vector(DDR3_RD_ADDR(15 downto 8));
	SREG(13) <= std_logic_vector(DDR3_RD_ADDR(7 downto 0));
	SREG(14) <= DDR3_DATA1_OUT_ADDR(31 downto 24);
	SREG(15) <= DDR3_DATA1_OUT_ADDR(23 downto 16);
	SREG(16) <= DDR3_DATA1_OUT_ADDR(15 downto 8);
	SREG(17) <= DDR3_DATA1_OUT_ADDR(7 downto 0);
	SREG(18) <= DDR3_DATA1_OUT_CEILINGADDR(31 downto 24);
	SREG(19) <= DDR3_DATA1_OUT_CEILINGADDR(23 downto 16);
	SREG(20) <= DDR3_DATA1_OUT_CEILINGADDR(15 downto 8);
	SREG(21) <= DDR3_DATA1_OUT_CEILINGADDR(7 downto 0);
	SREG(22) <= std_logic_vector(to_unsigned(DDR3_TEST_STATE,8));

VHDL simulation does not seem to show any problem. Only runtime execution.