-------------------------------------------------------------
-- MSS copyright 2015
-- Filename:  tbcom1800_ddr3.VHD
-- Authors: 
--		Alain Zarembowitch / MSS
-- Version: Rev 0
-- Last modified: 7/20/15
-- Inheritance: 	n/a
--
-- testbench for interfacing with DDR3 memory
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tbcom1800_ddr3 IS
END tbcom1800_ddr3;
 
ARCHITECTURE behavior OF tbcom1800_ddr3 IS 
 
--------------------------------------------------------
--      COMPONENTS
--------------------------------------------------------
 
    COMPONENT COM1800_TOP
	generic (
		DDR3_NRANKS: integer;
		OPTION: std_logic_vector(7 downto 0);    
		REVISION: std_logic_vector(7 downto 0);    
		SIMULATION: std_logic 
	);
    PORT(
         CLKREF_TCXO : IN  std_logic;
         CLKREF_EXT : IN  std_logic;
         LAN_TXC : OUT  std_logic;
         LAN_TXD : OUT  std_logic_vector(3 downto 0);
         LAN_TX_CTL : OUT  std_logic;
         LAN_RXC : IN  std_logic;
         LAN_RXD : IN  std_logic_vector(3 downto 0);
         LAN_RX_CTL : IN  std_logic;
         LAN_RESET_N : OUT  std_logic;
         LAN_MCLK : OUT  std_logic;
         LAN_MDIO : INOUT  std_logic;
         LAN_CLK125 : IN  std_logic;
         LAN_INT_N : IN  std_logic;
         ddr3_dq : INOUT  std_logic_vector(63 downto 0);
         ddr3_dqs_p : INOUT  std_logic_vector(7 downto 0);
         ddr3_dqs_n : INOUT  std_logic_vector(7 downto 0);
         ddr3_addr : OUT  std_logic_vector(15 downto 0);
         ddr3_ba : OUT  std_logic_vector(2 downto 0);
         ddr3_ras_n : OUT  std_logic;
         ddr3_cas_n : OUT  std_logic;
         ddr3_we_n : OUT  std_logic;
         ddr3_reset_n : OUT  std_logic;
			ddr3_ck_p : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
			ddr3_ck_n : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
			ddr3_cke  : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
			ddr3_cs_n : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
			ddr3_odt  : out   std_logic_vector((DDR3_NRANKS-1) downto 0);
         ddr3_dm : OUT  std_logic_vector(7 downto 0);
         LEFT_CONNECTOR_A : INOUT  std_logic_vector(38 downto 1);
         LEFT_CONNECTOR_B1 : INOUT  std_logic_vector(4 downto 1);
         LEFT_CONNECTOR_B2 : INOUT  std_logic_vector(16 downto 6);
         RIGHT_CONNECTOR_A : INOUT  std_logic_vector(38 downto 1);
         RIGHT_CONNECTOR_B1 : INOUT  std_logic_vector(4 downto 1);
         RIGHT_CONNECTOR_B2 : INOUT  std_logic_vector(19 downto 6);
         RIGHT_CONNECTOR_B3 : INOUT  std_logic_vector(30 downto 21);
         RIGHT_CONNECTOR_B4 : INOUT  std_logic_vector(39 downto 32);
         UC_CSIB_IN : IN  std_logic;
         UC_ALE_IN : IN  std_logic;
         UC_REB_IN : IN  std_logic;
         UC_WEB_IN : IN  std_logic;
         UC_AD : INOUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

--------------------------------------------------------
--     SIGNALS
--------------------------------------------------------
	constant DDR3_NRANKS: integer := 2;

   signal CLKREF_TCXO : std_logic := '0';
   signal CLKREF_EXT : std_logic := '0';
   signal LAN_RXC : std_logic := '0';
   signal LAN_RXD : std_logic_vector(3 downto 0) := (others => '0');
   signal LAN_RX_CTL : std_logic := '0';
   signal LAN_CLK125 : std_logic := '0';
   signal LAN_INT_N : std_logic := '0';
   signal UC_CSIB_IN : std_logic := '0';
   signal UC_ALE_IN : std_logic := '0';
   signal UC_REB_IN : std_logic := '0';
   signal UC_WEB_IN : std_logic := '0';

	--BiDirs
   signal LAN_MDIO : std_logic;
   signal ddr3_dq : std_logic_vector(63 downto 0);
   signal ddr3_dqs_p : std_logic_vector(7 downto 0);
   signal ddr3_dqs_n : std_logic_vector(7 downto 0);
   signal LEFT_CONNECTOR_A : std_logic_vector(38 downto 1);
   signal LEFT_CONNECTOR_B1 : std_logic_vector(4 downto 1);
   signal LEFT_CONNECTOR_B2 : std_logic_vector(16 downto 6);
   signal RIGHT_CONNECTOR_A : std_logic_vector(38 downto 1);
   signal RIGHT_CONNECTOR_B1 : std_logic_vector(4 downto 1);
   signal RIGHT_CONNECTOR_B2 : std_logic_vector(19 downto 6);
   signal RIGHT_CONNECTOR_B3 : std_logic_vector(30 downto 21);
   signal RIGHT_CONNECTOR_B4 : std_logic_vector(39 downto 32);
   signal UC_AD : std_logic_vector(7 downto 0);

 	--Outputs
   signal LAN_TXC : std_logic;
   signal LAN_TXD : std_logic_vector(3 downto 0);
   signal LAN_TX_CTL : std_logic;
   signal LAN_RESET_N : std_logic;
   signal LAN_MCLK : std_logic;
   signal ddr3_addr : std_logic_vector(15 downto 0);
   signal ddr3_ba : std_logic_vector(2 downto 0);
   signal ddr3_ras_n : std_logic;
   signal ddr3_cas_n : std_logic;
   signal ddr3_we_n : std_logic;
   signal ddr3_reset_n : std_logic;
   signal ddr3_ck_p : std_logic_vector((DDR3_NRANKS-1) downto 0);
   signal ddr3_ck_n : std_logic_vector((DDR3_NRANKS-1) downto 0);
   signal ddr3_cke : std_logic_vector((DDR3_NRANKS-1) downto 0);
   signal ddr3_cs_n : std_logic_vector((DDR3_NRANKS-1) downto 0);
   signal ddr3_dm : std_logic_vector(7 downto 0);
   signal ddr3_odt : std_logic_vector((DDR3_NRANKS-1) downto 0);

   -- Clock period definitions
   constant CLKREF_TCXO_period : time := 10 ns;
   constant CLKREF_EXT_period : time := 10 ns;
   constant LAN_MCLK_period : time := 10 ns;
 
--------------------------------------------------------
--      IMPLEMENTATION
--------------------------------------------------------
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: COM1800_TOP 
	GENERIC MAP (
		DDR3_NRANKS => DDR3_NRANKS,
		OPTION => x"41",    -- 'A'  
		REVISION => x"31",    
		SIMULATION => '1' 
	)
	
	PORT MAP (
          CLKREF_TCXO => CLKREF_TCXO,
          CLKREF_EXT => CLKREF_EXT,
          LAN_TXC => LAN_TXC,
          LAN_TXD => LAN_TXD,
          LAN_TX_CTL => LAN_TX_CTL,
          LAN_RXC => LAN_RXC,
          LAN_RXD => LAN_RXD,
          LAN_RX_CTL => LAN_RX_CTL,
          LAN_RESET_N => LAN_RESET_N,
          LAN_MCLK => LAN_MCLK,
          LAN_MDIO => LAN_MDIO,
          LAN_CLK125 => LAN_CLK125,
          LAN_INT_N => LAN_INT_N,
          ddr3_dq => ddr3_dq,
          ddr3_dqs_p => ddr3_dqs_p,
          ddr3_dqs_n => ddr3_dqs_n,
          ddr3_addr => ddr3_addr,
          ddr3_ba => ddr3_ba,
          ddr3_ras_n => ddr3_ras_n,
          ddr3_cas_n => ddr3_cas_n,
          ddr3_we_n => ddr3_we_n,
          ddr3_reset_n => ddr3_reset_n,
          ddr3_ck_p => ddr3_ck_p,
          ddr3_ck_n => ddr3_ck_n,
          ddr3_cke => ddr3_cke,
          ddr3_cs_n => ddr3_cs_n,
          ddr3_dm => ddr3_dm,
          ddr3_odt => ddr3_odt,
          LEFT_CONNECTOR_A => LEFT_CONNECTOR_A,
          LEFT_CONNECTOR_B1 => LEFT_CONNECTOR_B1,
          LEFT_CONNECTOR_B2 => LEFT_CONNECTOR_B2,
          RIGHT_CONNECTOR_A => RIGHT_CONNECTOR_A,
          RIGHT_CONNECTOR_B1 => RIGHT_CONNECTOR_B1,
          RIGHT_CONNECTOR_B2 => RIGHT_CONNECTOR_B2,
          RIGHT_CONNECTOR_B3 => RIGHT_CONNECTOR_B3,
          RIGHT_CONNECTOR_B4 => RIGHT_CONNECTOR_B4,
          UC_CSIB_IN => UC_CSIB_IN,
          UC_ALE_IN => UC_ALE_IN,
          UC_REB_IN => UC_REB_IN,
          UC_WEB_IN => UC_WEB_IN,
          UC_AD => UC_AD
        );

   -- Clock process definitions
   CLKREF_TCXO_process :process
   begin
		CLKREF_TCXO <= '0';
		wait for CLKREF_TCXO_period/2;
		CLKREF_TCXO <= '1';
		wait for CLKREF_TCXO_period/2;
   end process;
 
   CLKREF_EXT_process :process
   begin
		CLKREF_EXT <= '0';
		wait for CLKREF_EXT_period/2;
		CLKREF_EXT <= '1';
		wait for CLKREF_EXT_period/2;
   end process;
 
   LAN_MCLK_process :process
   begin
		LAN_MCLK <= '0';
		wait for LAN_MCLK_period/2;
		LAN_MCLK <= '1';
		wait for LAN_MCLK_period/2;
   end process;
 

   -- Stimulus process
--   stim_proc: process
--   begin		
--		UC_CSIB_IN <= '0';
--		UC_ALE_IN <= '0';
--		UC_REB_IN <= '1';
--		UC_WEB_IN <= '1';
--		UC_AD <= x"0a";
--		wait for 66 us;
--		UC_ALE_IN <= '1';
--		UC_WEB_IN <= '0';
--		wait for 10 ns;
--		UC_WEB_IN <= '1';
--		wait for 10 ns;
--		UC_ALE_IN <= '0';
--		UC_AD <= x"01";	-- start read (write 0x01 to REG10
--		UC_WEB_IN <= '0';
--		wait for 10 ns;
--		UC_WEB_IN <= '1';
--      wait;
--   end process;

END;
