Each ComBlock FPGA/VHDL development platform comes with a template project.
It is not only simpler, but also important, to start with the template project as several of the essential external communication functions are included in the template.
Xilinx ISE is a comprehensive development environment which allows users to go from VHDL source code to bit file. The free version of Xilinx ISE (WebPACK) can be downloaded from Xilinx. Please note that the more complex Comblock FPGA/VHDL development platforms require the Xilinx ISE Logic Edition.
The Xilinx ISE tools process the VHDL source code in successive steps ending with the generation of a .bit file:
- Synthesis
- Implementation: translate, map, place and route
- Bit file generation
The binary .bit file must then be converted to a .mcs text file. The instructions to generate a mcs file from a Xilinx ISE project are described in this document.
Multiple FPGA configurations (personalities) can be stored within a ComBlock Flash memory at any given time. From the ComBlock Control Center click on the Swiss army knife button to load, list and modify the personalities. See this document (Step 7) for more details.
| Troubleshooting |
Most Likely Remedy |
Is the DONE test point high? |
The DONE test point goes high (2.5 or 3.3V) after the FPGA has verified the configuration file integrity. This does not mean that the configuration file will work, just that it was not corrupted during transmission or flash programming. |
After loading a .mcs file, the board stopped responding |
Make sure the .ucf constraint file is included in the Xilinx ISE project, otherwise FPGA pins may be assigned randomly to nets.
Using the "create timing constraints' Xilinx utility, verify that all the I/Os used in the design are assigned FPGA pins. For convenience, most pins are declared (but possibly commented out) in the .ucf constraint file.
Make sure the interface with the Atmel 8-bit AVR microcontroller (included in the template) has not been modified. |
After loading a .mcs file, the COM-1000/8000/1100 board stopped responding. How to recover? |
Communication is restored by preventing the FPGA from being configured with the offending .mcs file. To do so, hold the INIT test point to ground for 7 seconds during power up. Do not turn power off until a valid FPGA configuration has been reprogrammed. |
After loading a .mcs file, the COM-1400/1300/1200 board stopped responding. How to recover? |
Communication is restored by switching to the protected configuration at personality index 1. To do so, connect a jumper between the BOOT pin and the adjacent pin before, during and 3 seconds after power up. |
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