Bit Interleaver COM-1016 -> DSSS modulator COM-1019 -> 
DSSS demodulator COM-1018 -> Bit Deinterleaver COM-1016 -> BER measurement COM-1005.


Test configuration example: 3.06 Mbit/s, 19.8 Mchip/s, processing gain 13, QPSK. 

The bit interleaver is placed in signal generator test mode, 
whereby a periodic 2047-bit sequence (PRBS-11) is being transmitted. 
The resulting data stream is bit interleaved, DSSS modulated to 19.9 Mchip/s, 
DSSS demodulated and bit deinterleaved. The end to end BER is measured using the 
COM-1005 module. The registers settings are as follows:

Proper operation can be verified as follows:

(a) using an oscilloscope probe:

COM-1001 TP1 is high, indicating demodulator carrier lock 

COM-1005 TP1 is high, indicating synchronization with the 2047-bit periodic test pattern 

COM-1005 TP3 is low, showing no bit error pulse.


(b) from the ComBlock control center check the BER (COM-1005 status).
It will show no bit errors (REG 1 through 4) and the synchronization bit (REG5 bit0) is high.
Depending on the demodulated phase ambiguity, the BER can be either 0 (no inverted bit) 
or 0x0F4240 (all bits inverted).