Overview
- Convolutional FEC codec, including encoder and Viterbi block decoder
- This codec operates in block mode, whereby a finite length frame is encoded and decoded. The error correction configuration (K, rate, polynomials, puncturing) can be changed dynamically on a frame-by-frame basis
- The code can be configured for either high speed (1 encoded bit per clock period) or small footprint
- When configured in parallel mode, the maximum throughput is typically in the range 100 – 250 Mbits/s depending on the FPGA technology
- Flexible dynamic (i.e. at runtime) user-selected configuration:
- Constraint length K=5,6,7,9
- Number of parity bits 2 to 5
- Gx generator polynomial from a preset list
- Puncturing pattern from a preset list
- GMR-1 3G compatible
- Built-in test tools: PRBS-11 test sequence generator, Bit Error Rate tester
- VHDL source code included
Documentation
Specifications
Complete VHDL/IP Core license agreement
Related products
Other error correction IP cores